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TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
Table3-7.PLL2SupportedClockingConfigurationsforDM355-270(24MHzreference)(continued)
PREDIVPLLMPOSTDIVPLL2VCODDRPHYDDRClock
810813241324162
810213061306153
89612881288144
1213312661266133
1210012001200100
151001160116080
3.5.3.2SupportedClockingConfigurationsforDM355-270(36MHzreference)
3.5.3.2.1DM355-270PLL1(36MHzreference)
AllsupportedclockingconfigurationsforDM355-270PLL1with36MHzreferenceclockareshownin
Table3-4
Table3-8.PLL1SupportedClockingConfigurationsforDM355-270(36MHzreference)
PREDIPLLMPOSTDIPLL1ARM/PeripheralsVencVPSS
VVVCOMPEGand
JPEG
Co-Processor
(/8(m(/2fixed)(MHz)PLLDIVSYSCPLLDIVSYSCLK2PLLDIV3SYSCLPLLDIV4SYSCLK4
fixed)programmable)1LK12(MHz)(/nK3(/2fixed)(MHz)
(/2(MHz)(/4programmable)(MHz)
fixed)fixed)
bypasbypassbypassbypas21849103.6418
ss
812015402270413520274135
811415132256.54128.2519274128.25
8108148622434121.518274121.5
810214592229.54114.7517274114.75
89624322216410816274108
818024052202.54101.2515272202.5
816823782189494.514272189
815623512175.5487.7513272175.5
81442324216248112272162
813222972148.5474.2511272148.5
812022702135467.510272135
810822432121.5460.759272121.5
896221621084548272108
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