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3.5.3SupportedClockingConfigurationsforDM355-270
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
ThissectiondescribestheonlysupporteddeviceclockingconfigurationsforDM355-270.TheDM355
supportseither24MHz(typical)or36MHzreferenceclock(crystalorexternaloscillatorinput).
Configurationsareshownforbothcases.
3.5.3.1SupportedClockingConfigurationsforDM355-270(24MHzreference)
3.5.3.1.1DM355-270PLL1(24MHzreference)
AllsupportedclockingconfigurationsforDM355-270PLL1with24MHzreferenceclockareshownin
Table3-2
Table3-6.PLL1SupportedClockingConfigurationsforDM355-270(24MHzreference)
PREDPLLMPOSTDIVPLL1ARM/PeripheralsVencVPSS
IVVCOMPEGandJPEG
Co-Processor
(/8(m(/2fixed)(MHz)PLLDIV1SYSCPLLDISYSCLK2PLLDIV3SYSCLKPLLDIV4SYSCLK4
fixed)programmable)(/2fixed)LK1V2(MHz)(/n3(/2fixed)(MHz)
(MHz)(/4programmable)(MHz)
fixed)
bypasbypassbypassbypas21246102.446
ss
818015402270413520274135
817115132256.54128.2519274128.25
8162148622434121.518274121.5
815314592229.54114.7517274114.75
814414322216410816274108
813514052202.54101.2515274101.25
812613782189494.51427494.5
811713512175.5487.751327487.75
8108132421624811227481
89912972148.5474.251127474.25
818022702135467.510272135
816222432121.5460.759272121.5
8144221621084548272108
81262189294.5447.25727294.5
81082162281440.5627281
3.5.3.1.2DM355-270PLL2(24MHzreference)
AllsupportedclockingconfigurationsforDM355-270PLL2with24MHzreferenceclockareshownin
Table3-3
Table3-7.PLL2SupportedClockingConfigurationsforDM355-270(24MHzreference)
PREDIVPLLMPOSTDIVPLL2VCODDRPHYDDRClock
(/nprogrammable)(m(/1fixed)(MHz)PLLDIV1SYSCLK1DDR_CLK
programmable)(/1fixed)(MHz)(MHz)
bypassbypassbypassbypass12412
814414321432216
813814141414207
813213961396198
812613781378189
812013601360180
811413421342171
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