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3.6PLLController(PLLC)
3.6.1PLLControllerModule
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
ThissectiondescribesthePLLControllersforPLL1andPLL2.SeetheTMS320DM355DigitalMedia
System-on-ChipARMSubsystemUser'sGuideformoreinformationonthePLLcontrollers.
TheDM355hastwoPLLcontrollersthatprovideclockstodifferentcomponentsofthechip.PLLcontroller
1(PLLC1)providesclockstomostofthecomponentsofthechip.PLLcontroller2(PLLC2)provides
clockstotheDDRPHY.
Asamodule,thePLLcontrollerprovidesthefollowing:
•Glitch-freetransitions(onchangingPLLsettings)
•Domainclocksalignment
•Clockgating
•PLLbypass
•PLLpowerdown
ThevariousclockoutputsgivenbythePLLcontrollerareasfollows:
•Domainclocks:SYSCLKn
•Bypassdomainclock:SYSCLKBP
•Auxiliaryclockfromreferenceclock:AUXCLK
Variousdividersthatcanbeusedareasfollows:
•Pre-PLLdivider:PREDIV
•Post-PLLdivider:POSTDIV
•SYSCLKdivider:PLLDIV1,…,PLLDIVn
•SYSCLKBPdivider:BPDIV
Multiplierssupportedareasfollows:
•PLLmultipliercontrol:PLLM
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