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Bit0 Bit(n-1) (n-2) (n-3) (n-4)
Bit0 Bit(n-1) (n-2) (n-3) (n-4)
M31
M30
M26M27
M25
M24
CLKX
FSX
DX
DR
M33
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
Table5-37.ASPasSPITimingRequirements
CLKSTP=10b,CLKXP=0(seeFigure5-42)
MASTER
NO.UNIT
MINMAX
M30t
su(DRV-CKXL)
Setuptime,DRvalidbeforeCLKXlow11ns
M31t
h(CKXL-DRV)
Holdtime,DRvalidafterCLKXlow0ns
Table5-38.ASPasSPISwitchingCharacteristics
(1)(2)
CLKSTP=10b,CLKXP=0(seeFigure5-42)
MASTER
NO.PARAMETERUNIT
MINMAX
38.5or
M33tc(CKX)Cycletime,CLKXns
2P
(1)(3)
M24t
d(CKXL-FXH)
Delaytime,CLKXlowtoFSXhigh
(2)
T–2T+3ns
M25t
d(FXL-CKXH)
Delaytime,FSXlowtoCLKXhigh
(4)
C–2C+2ns
M26t
d(CKXH-DXV)
Delaytime,CLKXhightoDXvalid–26ns
M27t
dis(CKXL-DXHZ)
Disabletime,DXhighimpedancefollowinglastdatabitfromCLKXlowC–3C+3ns
(1)P=(1/SYSCLK2),whereSYSCLK2isanoutputclockofPLLC1(seeSection3.5).
(2)T=BCLKXperiod=(1+CLKGDV)×2P
C=BCLKXlowpulsewidth=T/2whenCLKGDVisoddorzeroand=(CLKGDV/2)×2PwhenCLKGDViseven
(3)Usewhichevervalueisgreater.
(4)FSXshouldbelowbeforetherisingedgeofclocktoenableslavedevicesandthenbeginaSPItransferattherisingedgeofthemaster
clock(CLKX).
Figure5-42.ASPasSPI:CLKSTP=10b,CLKXP=0
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