Texas Instruments TMS320DM355 Computer Hardware User Manual


 
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PRODUCT PREVIEW
3.2.1CP15
3.2.2MMU
3.2.3CachesandWriteBuffer
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463ASEPTEMBER2007REVISEDSEPTEMBER2007
EmbeddedTraceModuleandEmbeddedTraceBuffer(ETM/ETB)
FormorecompletedetailsontheARM9,refertotheARM926EJ-STechnicalReferenceManual,available
athttp://www.arm.com
TheARM926EJ-Ssystemcontrolcoprocessor(CP15)isusedtoconfigureandcontrolinstructionand
datacaches,Tightly-CoupledMemories(TCMs),MemoryManagementUnit(MMU),andotherARM
subsystemfunctions.TheCP15registersareprogrammedusingtheMRCandMCRARMinstructions,
whentheARMinaprivilegedmodesuchassupervisororsystemmode.
TheARM926EJ-SMMUprovidesvirtualmemoryfeaturesrequiredbyoperatingsystemssuchasLinux,
WindowCE,ultron,ThreadX,etc.Asinglesetoftwolevelpagetablesstoredinmainmemoryisusedto
controltheaddresstranslation,permissionchecksandmemoryregionattributesforbothdataand
instructionaccesses.TheMMUusesasingleunifiedTranslationLookasideBuffer(TLB)tocachethe
informationheldinthepagetables.TheMMUfeaturesare:
StandardARMarchitecturev4andv5MMUmappingsizes,domainsandaccessprotectionscheme.
Mappingsizesare:
1MB(sections)
64KB(largepages)
4KB(smallpages)
1KB(tinypages)
Accesspermissionsforlargepagesandsmallpagescanbespecifiedseparatelyforeachquarterof
thepage(subpagepermissions)
Hardwarepagetablewalks
InvalidateentireTLB,usingCP15register8
InvalidateTLBentry,selectedbyMVA,usingCP15register8
LockdownofTLBentries,usingCP15register10
ThesizeoftheInstructionCacheis16KB,Datacacheis8KB.Additionally,theCacheshavethefollowing
features:
Virtualindex,virtualtag,andaddressedusingtheModifiedVirtualAddress(MVA)
Four-waysetassociative,withacachelinelengthofeightwordsperline(32-bytesperline)andwith
twodirtybitsintheDcache
Dcachesupportswrite-throughandwrite-back(orcopyback)cacheoperation,selectedbymemory
regionusingtheCandBbitsintheMMUtranslationtables.
Critical-wordfirstcacherefilling
Cachelockdownregistersenablecontroloverwhichcachewaysareusedforallocationonalinefill,
providingamechanismforbothlockdown,andcontrollingcachecorruption
DcachestoresthePhysicalAddressTAG(PATAG)correspondingtoeachDcacheentryintheTAG
RAMforuseduringthecachelinewrite-backs,inadditiontotheVirtualAddressTAGstoredinthe
TAGRAM.ThismeansthattheMMUisnotinvolvedinDcachewrite-backoperations,removingthe
possibilityofTLBmissesrelatedtothewrite-backaddress.
Cachemaintenanceoperationsprovideefficientinvalidationof,theentireDcacheorIcache,regionsof
theDcacheorIcache,andregionsofvirtualmemory.
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