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3.6.2PLLC1
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
PLLC1providesmostoftheDM355clocks.SoftwarecontrolsPLLC1operationthroughthePLLC1
registers.Thefollowinglist,Table3-10,andFigure3-3describethecustomizationsofPLLC1inthe
DM355.
•ProvidesprimaryDM355systemclock
•Softwareconfigurable
•Acceptsclockinputorinternaloscillatorinput
•PLLpre-dividervalueisfixedto(/8)
•PLLmultipliervalueisprogrammable
•PLLpost-divider
•OnlySYSCLK[4:1]areused
•SYSCLK1dividervalueisfixedto(/2)
•SYSCLK2dividervalueisfixedto(/4)
•SYSCLK3dividervalueisprogrammable
•SYSCLK4dividervalueisprogrammableto(/4)or(/2)
•SYSCLKBPdividervalueisfixedto(/3)
•SYSCLK1isroutedtotheARMSubsystem
•SYSCLK2isroutedtoperipherals
•SYSCLK3isroutedtotheVPBEmodule
•SYSCLK4isroutedtotheVPSSmodule
•AUXCLKisroutedtoperipheralswithfixedclockdomainandalsototheoutputpinCLKOUT1
•SYSCLKBPisroutedtotheoutputpinCLKOUT2
Table3-10.PLLC1OutputClocks
OutputClockUsedByPLLDIVNotes
Divider
SYSCLK1ARMSubsystem/MPEGandJPEGCo-Processor/2Fixeddivider
SYSCLK2Peripherals/4Fixeddivider
SYSCLK3VPBE(VENCmodule)/nProgrammabledivider(usedtoget27
MHzforVENC)
SYSCLK4VPSS/4or/2Programmabledivider
AUXCLKPeripherals,CLKOUT1noneNodivider
SYSCLKBPCLKOUT2/3Fixeddivider
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