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2DeviceOverview
2.1DeviceCharacteristics
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
Table2-1providesanoverviewoftheDMSoC.Thetableshowssignificantfeaturesofthedevice,
includingtheperipherals,capacityofon-chipRAM,ARMoperatingfrequency,thepackagetypewithpin
count,etc.
Table2-1.CharacteristicsoftheProcessor
HARDWAREFEATURESDM355
DDR2/mDDRMemoryControllerDDR2/mDDR(16-bitbuswidth)
Asynchronous(8/16-bitbuswidth)
AsynchronousEMIF(AEMIF)
RAM,Flash(NAND,OneNAND)
TwoMMC/SD
FlashCardInterfaces
OneSmartMedia/xD
64independentDMAchannels
EDMA
EightEDMAchannels
Three64-BitGeneralPurpose(each
configurableastwoseparate32-bit
Timers
timers)
Peripherals
One64-BitWatchDog
Notallperipheralspinsare
Three(onewithRTSandCTSflow
availableatthesametime
UART
control)
(Formoredetail,seethe
DeviceConfiguration
Three(eachsupportstwoslave
SPI
section).
devices)
I
2
COne(Master/Slave)
AudioSerialPort[ASP]TwoASP
General-PurposeInput/OutputPortUpto104
Pulsewidthmodulator(PWM)Fouroutputs
OneInput(VPFE)
ConfigurableVideoPorts
OneOutput(VPBE)
High,FullSpeedDevice
USB2.0
High,Full,LowSpeedHost
ARM
On-ChipCPUMemoryOrganization16-KBI-cache,8-KBD-cache,
32-KBRAM,8-KBROM
JTAGBSDL_IDJTAGIDregister(addresslocation:0x01C40028)0x0B73B01F
CPUFrequency(Maximum)MHzARM216MHzand270MHz
Core(V)1.3V
Voltage
I/O(V)3.3V,1.8V
Referencefrequencyoptions24MHz(typical),36MHz
PLLOptions
ConfigurablePLLcontrollerPLLbypass,programmablePLL
BGAPackage13x13mm337-PinBGA(ZCE)
ProcessTechnology90nm
ProductPreview(PP),
ProductStatus
(1)
AdvanceInformation(AI),PP
orProductionData(PD)
(1)PRODUCTPREVIEWinformationconcernsproductsintheformativeordesignphaseofdevelopment.Characteristicdataandother
specificationsaredesigngoals.TexasInstrumentsreservestherighttochangeordiscontinuetheseproductswithoutnotice.
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