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5.14.1ASPElectricalData/Timing
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
5.14.1.1AudioSerialPort(ASP)Timing
Table5-35.TimingRequirementsforASP
(1)
(seeFigure5-41)
DM355
NO.UNIT
MINMAX
15tc(CLK)Cycletime,CLKCLKext38.5or2P
(2)(3)
ns
16OTG(CLKS)Pulseduration,CLKR/XhighorCLKR/XlowCLKSext19.25orP
(2)(3)(4)
ns
CLKRint21
5t
su(FRH-CKRL)
Setuptime,externalFSRhighbeforeCLKRlowns
CLKRext6
CLKRint0
6t
h(CKRL-FRH)
Holdtime,externalFSRhighafterCLKRlowns
CLKRext6
CLKRint21
7t
su(DRV-CKRL)
Setuptime,DRvalidbeforeCLKRlowns
CLKRext6
CLKRint0
8t
h(CKRL-DRV)
Holdtime,DRvalidafterCLKRlowns
CLKRext6
CLKXint21
10t
su(FXH-CKXL)
Setuptime,externalFSXhighbeforeCLKXlowns
CLKXext6
CLKXint0
11t
h(CKXL-FXH)
Holdtime,externalFSXhighafterCLKXlowns
CLKXext10
(1)CLKRP=CLKXP=FSRP=FSXP=0.Ifpolarityofanyofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso
inverted.
(2)P=(1/SYSCLK2),whereSYSCLK2isanoutputclockofPLLC1(seeSection3.5).
(3)Usewhichevervalueisgreater.
(4)TheASPdoesnothaveadutycyclespecification,justensurethattheminimumpulsedurationspecificationismet.
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