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Bit0 Bit(n-1) (n-2) (n-3) (n-4)
Bit0 Bit(n-1) (n-2) (n-3) (n-4)
M39
M36
M38
M37
M35
M34
CLKX
FSX
DX
DR
M40
M42
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
Table5-39.ASPasSPITimingRequirements
CLKSTP=11b,CLKXP=0
MASTER
NO.UNIT
MINMAX
M39t
su(DRV-CKXH)
Setuptime,DRvalidbeforeCLKXhigh11ns
M40t
h(CKXH-DRV)
Holdtime,DRvalidafterCLKXhigh1ns
Table5-40.ASPasSPISwitchingCharacteristics
(1)(2)
CLKSTP=11b,CLKXP=0(seeFigure5-43)
MASTER
NO.PARAMETERUNIT
MINMAX
38.5or
M42tc(CKX)Cycletime,CLKXns
2P
(1)(3)
M34t
d(CKXL-FXH)
Delaytime,CLKXlowtoFSXhigh
(4)
C–2C+3ns
M35t
d(FXL-CKXH)
Delaytime,FSXlowtoCLKXhigh
(5)
T–2T+2ns
M36t
d(CKXL-DXV)
Delaytime,CLKXlowtoDXvalid–26ns
Disabletime,DXhighimpedancefollowinglastdatabitfrom
M37t
dis(CKXL-DXHZ)
–33ns
CLKXlow
M38t
d(FXL-DXV)
Delaytime,FSXlowtoDXvalidD–2D+10ns
(1)P=(1/SYSCLK2),whereSYSCLK2isanoutputclockofPLLC1(seeSection3.5).
(2)T=CLKXperiod=(1+CLKGDV)×P
C=CLKXlowpulsewidth=T/2whenCLKGDVisoddorzeroand=(CLKGDV/2)×PwhenCLKGDViseven
D=CLKXhighpulsewidth=T/2whenCLKGDVisoddorzeroand=(CLKGDV/2+1)×PwhenCLKGDViseven
(3)Usewhichevervalueisgreater.
(4)FSRP=FSXP=1.AsaSPImaster,FSXisinvertedtoprovideactive-lowslave-enableoutput.
CLKXM=FSXM=1,CLKRM=FSRM=0formasterASP
(5)FSXshouldbelowbeforetherisingedgeofclocktoenableslavedevicesandthenbeginaSPItransferattherisingedgeofthemaster
clock(CLKX).
Figure5-43.ASPasSPI:CLKSTP=11b,CLKXP=0
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