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Glossary-3
PCI Peripheral component interconnect. A high-performance 32- or 64-bit-wide bus
with multiplexed address and data lines.
PCIO PCI-to-EBus/Ethernet controller. An ASIC that bridges the PCI bus to the
EBus, enabling communication between the PCI bus and all miscellaneous I/O
functions, as well as the connection to slower on-board functions.
PCMCIA Personal computer memory card international association.
PID Process ID.
POR Power-on reset.
POST Power-on self-test. A series of tests that verify system board components are
operating properly. Initialized at system power-on or when the system is
rebooted.
RAMDAC RAM digital-to-analog converter. An ASIC responsible for direct interface to
3DRAM. Also provides on-board phase-lock loop (PLL) and clock generator
circuitry for the pixel clock.
RC Resistive-capacitive.
RISC Reset, interrupt, scan, and clock. An ASIC responsible for reset, interrupt, scan,
and clock.
RMA Removable media assembly. Can include a CD-ROM drive or 4-mm, 8-mm, a
diskette drive, and any other 3.5-inch device, such as a second diskette drive or
a peripheral component interconnect (PCI) device.
SB Single buffer.
SCSI Small computer system interface.
SC_UP+ System controller uniprocessor plus. An ASIC that regulates the flow of
requests and data throughout the system unit.
STP Shielded twisted-pair.
SunVTS A diagnostic application designed to test hardware.
TPE Twisted-pair Ethernet.
TOD Time of day. A timekeeping intergrated circuit.
TTL Transistor-transistor logic.
U2P UPA-to-PCI. An ASIC that controls the PCI buses. It forms the bridge from the
UPA bus to the PCI buses.