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Glossary-4 Sun Ultra 60 Service Manual • August 2001
UPA UltraSPARC port architecture. Provides processor-to-memory interconnection.
UPAAD0 UPA address bus 0. Provides data interface between CPU module 0 and the
QSC ASIC.
UPAAD1 UPA address bus 1. Provides data interface between CPU module 1 and the
QSC ASIC.Supports slave UPA connection to the expansion slot for graphics
capability.
UPAAD2 UPA address bus 2. Provides data interface between QSC ASIC and the U2P
ASIC.
UPAAD3 UPA address bus 3. Provides data interface between QSC ASIC and the UPA
graphics.
UPADATA0 UPA data bus 0. Provides 144-bit-wide data bus between the XB9+ ASIC and
CPU module 0.
UPADATA1 UPA data bus 1. Provides 144-bit-wide data bus between the XB9+ ASIC and
the UPA graphics.
UPADATA2 UPA data bus 2. Provides 64-bit-wide data bus between the XB9+ ASIC and
CPU module 0.
UPADATA3 UPA data bus 3. Provides 72-bit-wide data bus between the XB9+ ASIC and the
U2P ASIC.
UTP Unshielded twisted-pair.
VIS Visual instruction set.
Vrms Volts root-mean-square.