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Chapter 3 Power-On Self-Test 3-17
0> <1f> Psycho Perf Cntl Reg Test
0> <1f> PIO Decoder and BCT Test
0> <1f> PCI Byte Enable Test
0> <1f> Counter/Timer Limit Regs Test
0> <1f> Timer Reload Test
0> <1f> Timer Periodic Test
0> <1f> Mondo Int Map (short) Reg Test
0> <1f> Mondo Int Set/Clr Reg Test
0> <1f> Psycho IOMMU Regs Test
0> <1f> Psycho IOMMU RAM Address Test
0> <1f> Psycho IOMMU CAM Address Test
0> <1f> IOMMU TLB Compare Test
0> <1f> IOMMU TLB Flush Test
0> <1f> Stream Buff A Control Reg Test
0> <1f> Psycho ScacheA Page Tag Addr Test
0> <1f> Psycho ScacheA Line Tag Addr Test
0> <1f> Psycho ScacheA RAM Addr Test
0> <1f> Psycho ScacheA Error Status NTA Test
0> <1f> Psycho ScacheB Page Tag Addr Test
0> <1f> Psycho ScacheB Line Tag Addr Test
0> <1f> Psycho ScacheB RAM Addr Test
0> <1f> Psycho ScacheB Error Status NTA Test
0> <1f> PBMA PCI Config Space Regs Test
0> <1f> PBMA Control/Status Reg Test
0> <1f> PBMA Diag Reg Test
0> <1f> PBMB PCI Config Space Regs Test
0> <1f> PBMB Control/Status Reg Test
0> <1f> PBMB Diag Reg Test
0> <00> UltraSPARC-2 Prefetch Instructions Test
0> <00>Test 0: prefetch_mr
0> <00>Test 1: prefetch to non-cacheable page
0> <00>Test 2: prefetch to page with dmmu misss
0> <00>Test 3: prefetch miss does not check alignment
0> <00>Test 4: prefetcha with asi 0x4c is noped
0> <00>Test 5: prefetcha with asi 0x54 is noped
0> <00>Test 6: prefetcha with asi 0x6e is noped
0> <00>Test 7: prefetcha with asi 0x76 is noped
0> <00>Test 8: prefetch with fcn 5
0> <00>Test 9: prefetch with fcn 2
0> <00>Test 10: prefetch with fcn 12
0> <00>Test 11: prefetch with fcn 16 is noped
0> <00>Test 12: prefetch with fcn 29 is noped
0> <00>Test 13: prefetcha with asi 0x15 is noped
0> <00>Test 14: prefetch with fcn 3
0> <00>Test 15: prefetcha14 with fcn 2
0> <00>Test 16: prefetcha80_mr
0> <00>Test 17: prefetcha81_1r
CODE EXAMPLE 3-2 diag-level Variable Set to min (Continued)