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138 AMD Geode™ SC1200/SC1201 Processor Data Book
SuperI/O Module
32579B
Table 5-53. Bank 6 Register Map
Offset Type Name
00h R/W IRCR3. IR Control 3
01h R/W MIR_PW. MIR Pulse Width
02h R/W SIR_PW. SIR Pulse Width
03h R/W BSR. Bank Select
04h R/W BFPL. Beginning Flags/Preamble Length
05h-07h --- RSVD. Reserved
Table 5-54. Bank 7 Register Map
Offset Type Name
00h R/W IRRXDC. IR Receiver Demodulator Control
01h R/W IRTXMC. IR Transmitter Modulator Control
02h R/W RCCFG. Consumer IR (CEIR) Configuration
03h R/W BSR. Bank Select
04h R/W IRCFG1. IR Interface Configuration 1
05h-06h --- RSVD. Reserved
07h R/W IRCFG4. IR Interface Configuration 4
Table 5-55. Bank 0 Bit Map
Register Bits
OffsetName76543210
00h RXD RXD[7:0] (Receive Data)
TXD TXD[7:0] (Transmit Data)
01h
IER
1
RSVD MS_IE LS_IE TXLDL_IE RXHDL_IE
IER
2
TMR_IE SFIF_IE TXEMP_
IE/PLD_IE
DMA_IE MS_IE LS_IE TXLDL_IE RXHDL_IE
02h
EIR
1
FEN[1:0] RSVD RXFT IPR[1:0] IPF
EIR
2
TMR_EV SFIF_EV TXEMP_EV/
PLD_EV
DMA_EV MS_EV LS_EV/
TXHLT_EV
TXLDL_EV RXHDL_EV
FCR RXFTH[1:0] TXFTH[1:0] RSVD TXSR RXSR FIFO_EN
03h LCR BKSE SBRK STKP EPS PEN STB WLS[1:0]
BSR BKSE BSR[6:0] (Bank Select)
04h
MCR
1
RSVD LOOP ISEN/
DCDLP
RILP RTS DTR
MCR
2
MDSL[2:0] IR_PLS TX_DFR DMA_EN RTS DTR
05h LSR ER_INF/
FR_END
TXEMP TXRDY BRK/
MAX_LEN
FE/
PHY_ERR
PE/
BAD_CRC
OE RXDA
06h MSR DCD RI DSR CTS DDCD TERI DDSR DCTS
07h
SPR
1
Scratch Data
ASCR
2
CTE/PLD TXUR RXACT/
RXBSY
RXWDG/
LOST_FR
TXHFE S_EOT FEND_INF RXF_TOUT
1. Non-extended mode.
2. Extended mode.