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342 AMD Geode™ SC1200/SC1201 Processor Data Book
Video Processor Module - Video Processor Registers - Function 4
32579B
Offset 1Ch-1Fh Palette (Gamma Correction RAM) Address Register (R/W) Reset Value: xxxxxxxxh
31:8 Reserved.
7:0 PAL_ADDR (Palette Address). Specifies the address to be used for the next access to the Palette Data register
(F4BAR0+Memory Offset 20h[31:8]). Each access to the data register automatically increments the Palette Address regis-
ter. If non-sequential access is made to the palette, the address register must be loaded between each non-sequential data
block.
Offset 20h-23h Palette (Gamma Correction RAM) Data Register (R/W) Reset Value: xxxxxxxxh
Provides the video palette data. The data can be read or written to the Gamma Correction RAM (palette) via this register. Prior to
accessing this register, an appropriate address should be loaded to the Palette Address register (F4BAR0+Memory Offset 1Ch[7:0]).
Subsequent accesses to the Palette Data register cause the internal address counter to be incremented for the next cycle.
31:8 PAL_DATA (Palette Data). Contains the read or write data for a Gamma Correction RAM (palette).
Blue[7:0] = Bits [31:24]
Green[7:0] = Bits [23:16]
Red[7:0] = Bits [15:8]
Note: When a read or write to the Gamma Correction RAM occurs, the previous output value is held for one additional
DOTCLK period. This effect should go unnoticed during normal operation.
7:0 Reserved.
Offset 24h-27h Reserved
Offset 28h-2Bh Miscellaneous Register (R/W) Reset Value: 00001400h
Configuration and control register for miscellaneous characteristics of the Video Processor.
31:13 Reserved.
12 PLL2_PWR_EN (PLL2 Power-Down Enable).
0: Power-down.
1: Normal.
11 A_PWR_DN (Analog Power-Down). Enables power-down of the PLL2 and the bandgap circuit that generates VREF.
0: Normal.
1: Power-down.
Note: If A_PWR_DN is set to 1 without also setting DAC_PWR_DN (bit 10) to 1, an unexpected increase in power con-
sumption may result.
10 DAC_PWR_DN (DAC Power-Down). Powers down the internal CRT DAC.
0: Normal.
1: Power-down.
9:1 Reserved.
0 GAMMA_EN (Gamma Correction RAM Enable). Allows video or graphics (selected by F4BAR0+Memory Offset 04h[21])
to go to the Gamma Correction RAM.
0: Enable.
1: Disable.
Offset 2Ch-2Fh PLL2 Clock Select Register (R/W) Reset Value: 00000000h
Determines the characteristics of the integrated PLL2.
31:23 Reserved. Must be set to 0.
22:21 CLK_DIV_SEL (Clock Divider Select).
00: No division
01: Divide by 2
10: Divide by 4
11: Divide by 8
Divides the clock generated by the PLL2, using the programmed m (bits [14:8]) and n (bits [3:0]) values.
20 SEL_REG_CAL. Selects specific or previously-calculated values.
0: Values previously calculated from the CLK_SEL bits (bits [19:16]).
1: Values according to the m (bits [14:8]), n (bits [3:0]), and CLK_DIV_SEL (bits [22:21]) fields.
Table 7-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit Description