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178 AMD Geode™ SC1200/SC1201 Processor Data Book
Core Logic Module - Register Summary
32579B
B8h 8 RO DMA Shadow Register xxh Page 217
B9h 8 RO PIC Shadow Register xxh Page 217
BAh 8 RO PIT Shadow Register xxh Page 217
BBh 8 RO RTC Index Shadow Register xxh Page 218
BCh 8 R/W Clock Stop Control Register 00h Page 218
BDh-BFh --- --- Reserved 00h Page 218
C0h-C3h 32 R/W User Defined Device 1 Base Address Register 00000000h Page 218
C4h-C7h 32 R/W User Defined Device 2 Base Address Register 00000000h Page 218
C8h-CBh 32 R/W User Defined Device 3 Base Address Register 00000000h Page 218
CCh 8 R/W User Defined Device 1 Control Register 00h Page 219
CDh 8 R/W User Defined Device 2 Control Register 00h Page 219
CEh 8 R/W User Defined Device 3 Control Register 00h Page 219
CFh --- --- Reserved 00h Page 219
D0h 8 WO Software SMI Register 00h Page 219
D1h-EBh 16 --- Reserved 00h Page 219
ECh 8 R/W Timer Test Register 00h Page 220
EDh-F3h --- --- Reserved 00h Page 220
F4h 8 RC Second Level PME/SMI Status Register 1 00h Page 220
F5h 8 RC Second Level PME/SMI Status Register 2 00h Page 220
F6h 8 RC Second Level PME/SMI Status Register 3 00h Page 221
F7h 8 RC Second Level PME/SMI Status Register 4 00h Page 222
F8h-FFh --- --- Reserved 00h Page 223
Table 6-14. F0: PCI Header/Bridge Configuration Registers for
GPIO and LPC Support Summary (Continued)
F0 Index
Width
(Bits) Type Name
Reset
Value
Reference
(Table 6-29)