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AMD Geode™ SC1200/SC1201 Processor Data Book 161
Core Logic Module
32579B
Power Button
The power button (PWRBTN#) input provides two events: a
wake request, and a sleep request. For both these events,
the PWRBTN# signal is debounced (i.e., the signal state is
transferred only after 14 to 16 ms without transitions, to
ensure that the signal is no longer bouncing).
ACPI is non-functional and all ACPI outputs are undefined
when the power-up sequence does not include using the
power button. SUSP# is an internal signal generated from
the ACPI block. Without an ACPI reset, SUSP# can be per-
manently asserted. If the USE_SUSP bit in CCR2 of GX1
module is enabled (Index C2h[7] = 1), the CPU will stop.
If ACPI functionality is desired, or the situation described
above avoided, the power button must be toggled. This can
be done externally or internally. GPIO63 is internally con-
nected to PWRBTN#. To toggle the power button with soft-
ware, GPIO63 must be programmed as an output using the
normal GPIO programming protocol (see Section 6.4.1.1
"GPIO Support Registers" on page 224). GPIO63 must be
pulsed low for at least 16 ms and not more than 4 sec.
Asserting POR# has no effect on ACPI. If POR# is
asserted and ACPI was active prior to POR#, then ACPI
will remain active after POR#. Therefore, BIOS must
ensure that ACPI is inactive before GPIO63 is pulsed low.
Power Button Wake Event - Detection of a high-to-low
transition on the debounced PWRBTN# input signal when
in SL1 to SL5 Sleep states. The system is considered in
the Sleep state, only after it actually transitioned into the
state and not only according to the SLP_TYP field.
In reaction to this event, the PWRBTN_STS bit (F1BAR1+I/
O Offset 08h[8]) is set to 1 and a wakeup event or an inter-
rupt is generated (note that this is regardless of the
PWRBTN_EN bit, F1BAR1+I/O Offset 0Ah[8]).
Power Button Sleep Event - Detection of a high-to-low
transition on the debounced PWRBTN# input signal, when
in the Working state (S0).
In reaction to this event, the PWRBTN_STS bit is set to 1.
• When both the PWRBTN_STS bit and the
PWRBTN_EN bit are set to 1, an SCI interrupt is gener-
ated.
• When SCI_EN bit is 0, ONCTL# and PWRCNT[2:1] are
de-asserted immediately regardless of the
PWRBTN_EN bit.
Power Button Override
When PWRBTN# is 0 for more than four seconds, ONCTL#
and PWRCNT[2:1] are de-asserted (i.e., the system transi-
tions to the SL5 state, “Soft Off”). This power management
event is called the power button override event.
In reaction to this event, the PWRBTN_STS bit is cleared
to 0 and the PWRBTNOR_STS bit (F1BAR1+I/O Offset
08h[11]) is set to 1.
Thermal Monitoring
The thermal monitoring event (THRM#) enables control of
ACPI-OS Control.
When the THRM# signal transitions from high-to-low, the
THRM_STS bit (F1BAR1+I/O Offset 10h[5]) is set to 1. If
the THRM_EN bit (F1BAR1+I/O Offset 12h[5]) is also set
to 1, an interrupt is generated.
SDATA_IN2, IRRX1, RI2#
Section 5.4.1 "SIO Control and Configuration Registers" on
page 97 for control and operation.
6.2.9.5 Usage Hints
• During initialization, the BIOS should:
— Clear the SUSP_HLT bit in CCR2 (GX1 module,
Index C2h[3]) to 0. This is needed for compliance
with C0 definition of ACPI, when the Halt Instruction
(HLT) is executed.
— Disable the SUSP_3V option in C3 power state (F0
Index 60h[2]).
— Disable the SUSP_3V option in SL1 sleep state (F0
Index 60h[1]).
• SMM code should clear the CLK_STP bit in the PM
Clock Stop Control register (GX_BASE+Memory Offset
8500h[0]) to 0 when entering C3 state.
• SMM code should correctly set the CLK_STP bit in the
PM Clock Stop Control register (GX_BASE+Memory
Offset 8500h[0]) when entering the SL1, SL2, and SL3
states.