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308 AMD Geode™ SC1200/SC1201 Processor Data Book
Core Logic Module - ISA Legacy Register Space
32579B
Table 6-48. Real-Time Clock Registers
Bit Description
I/O Port 070h RTC Address Register (WO)
This register is shadowed within the Core Logic module and is read through the RTC Shadow Register (F0 Index BBh).
7 NMI Mask.
0: Enable.
1: Mask.
6:0 RTC Register Index. A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered.
(RTCALE is an internal signal between the Core Logic module and the internal RTC controller.)
I/O Port 071h RTC Data Register (R/W)
A read of this register returns the value of the register indexed by the RTC Address Register.
A write of this register sets the value into the register indexed by the RTC Address Register
I/O Port 072h RTC Extended Address Register (WO)
7 Reserved.
6:0 RTC Register Index. A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered.
(RTCALE is an internal signal between the Core Logic module and the internal RTC controller.)
I/O Port 073h RTC Data Register (R/W)
AA read of this register returns the value of the register indexed by the RTC Extended Address Register.
A write of this register sets the value into the register indexed by the RTC Extended Address Register
Table 6-49. Miscellaneous Registers
Bit Description
I/O Port 0F0h, 0F1h Coprocessor Error Register (W) Reset Value: F0h
A write to either port when the internal FERR# signal is asserted causes the Core Logic Module to assert internal IGNNE#. IGNNE#
remains asserted until the FERR# de-asserts.
I/O Ports 170h-177h/376h-377h Secondary IDE Registers (R/W)
When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate according to
their configuration rather than generating standard ISA bus cycles.
I/O Ports 1F0h-1F7h/3F6h-3F7h Primary IDE Registers (R/W)
When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate according to
their configuration rather than generating standard ISA bus cycles.
I/O Port 4D0h Interrupt Edge/Level Select Register 1 (R/W) Reset Value: 00h
Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides the setting for bits [7:3] in this register.
2. Bits [7:3] in this register are used to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared).
7 IRQ7 Edge or Level Sensitive Select. Selects PIC IRQ7 sensitivity configuration.
0: Edge.
1: Level.
6 IRQ6 Edge or Level Sensitive Select. Selects PIC IRQ6 sensitivity configuration.
0: Edge.
1: Level.
5 IRQ5 Edge or Level Sensitive Select. Selects PIC IRQ5 sensitivity configuration.
0: Edge.
1: Level.
4 IRQ4 Edge or Level Sensitive Select. Selects PIC IRQ4 sensitivity configuration.
0: Edge.
1: Level.
3 IRQ3 Edge or Level Sensitive Select. Selects PIC IRQ3 sensitivity configuration.
0: Edge.
1: Level.