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34 AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
32579B
J2 C/BE1# I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D9 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
J3 AD15 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A15 O O
PCI
J4 PAR I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D12 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
J28 VPD2 I IN
T
V
IO
---
J29 VPD1 I IN
T
V
IO
---
J30 VPD0 I IN
T
V
IO
---
J31 GPIO39 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
4
= 0 and
PMR[22]
4
= 0
SERIRQ I/O IN
PCI
,
O
PCI
PMR[14]
4
= 1 and
PMR[22]
4
= 1
K1 AD11 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A11 O O
PCI
K2 V
IO
PWR --- --- ---
K3 V
SS
GND --- --- ---
K4 AD14 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A14 O O
PCI
K28 GPIO38/IRRX2 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
4
= 0 and
PMR[22]
4
= 0. The
IRRX2 input is con-
nected to the input
path of GPIO38.
There is no logic
required to enable
IRRX2, just a sim-
ple connection.
Hence, when
GPIO38 is the
selected function,
IRRX2 is also
selected.
LPCPD# O O
PCI
PMR[14]
4
= 1 and
PMR[22]
4
= 1
K29 V
IO
PWR --- --- ---
K30 V
SS
GND --- --- ---
K31 GPIO37 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
4
= 0 and
PMR[22]
4
= 0
LFRAME# O O
PCI
PMR[14]
4
= 1 and
PMR[22]
4
= 1
L1 C/BE0# I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D8 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
L2 AD9 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A9 O O
PCI
Ball
No. Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail Configuration
L3 AD10 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A10 O O
PCI
L4 AD12 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A12 O O
PCI
L28 GPIO36 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
4
= 0 and
PMR[22]
4
= 0
LDRQ# I IN
PCI
PMR[14]
4
= 1 and
PMR[22]
4
= 1
L29 GPIO35 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
4
= 0 and
PMR[22]
4
= 0
LAD3 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14]
4
= 1 and
PMR[22]
4
= 1
L30 GPIO34 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
4
= 0 and
PMR[22]
4
= 0
LAD2 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14]
4
= 1 and
PMR[22]
4
= 1
L31 GPIO33 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
4
= 0 and
PMR[22]
4
= 0
LAD1 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14]
4
= 1 and
PMR[22]
4
= 1
M1 V
SS
GND --- --- ---
M2 AD7 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A7 O O
PCI
M3 V
IO
PWR --- --- ---
M4 AD8 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A8 O O
PCI
M28 GPIO32 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
4
= 0 and
PMR[22]
4
= 0
LAD0 I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14]
4
= 1 and
PMR[22]
4
= 1
M29 GPIO13 I/O
(PU
22.5
)
IN
AB
,
O
8/8
V
IO
PMR[19] = 0
AB2D I/O
(PU
22.5
)
IN
AB
,
OD
8
V
IO
PMR[19] = 1
M30 V
IO
PWR --- --- ---
M31 V
SS
GND --- --- ---
N1 AD3 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A3 O O
PCI
N2 AD6 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A6 O O
PCI
N3 AD5 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A5 O O
PCI
N4 V
SS
GND --- --- ---
N13 V
CORE
PWR --- --- ---
N14 V
CORE
PWR --- --- ---
Ball
No. Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail Configuration
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)