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32 AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Definitions
32579B
C30 GPIO7 I/O
(PU
22.5
)
IN
TS
,
O
1/4
V
IO
PMR[17] = 0 and
PMR[8] = 0
RTS2# O
(PU
22.5
)
O
1/4
PMR[17] = 1 and
PMR[8] = 0
IDE_DACK1# O
(PU
22.5
)
O
1/4
PMR[17] = 0 and
PMR[8] = 1
SDTEST0 O
(PU
22.5
)
O
2/5
PMR[17] = 1 and
PMR[8] = 1
C31 GPIO8 I/O
(PU
22.5
)
IN
TS
,
O
8/8
V
IO
PMR[17] = 0 and
PMR[8] = 0
CTS2# I
(PU
22.5
)
IN
TS
PMR[17] = 1 and
PMR[8] = 0
IDE_DREQ1 I
(PU
22.5
)
IN
TS1
PMR[17] = 0 and
PMR[8] = 1
SDTEST4 O
(PU
22.5
)
O
2/5
PMR[17] = 1 and
PMR[8] = 1
D1 AD21 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A21 O O
PCI
D2 AD22 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A22 O O
PCI
D3 AD20 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A20 O O
PCI
D4 AD27 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D3 I/O IN
PCI
,
O
PCI
D5 AD31 I/O IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D7 I/O IN
PCI
,
O
PCI
D6 PCICLK1 O O
PCI
V
IO
---
LPC_ROM I
(PD
100
)
IN
STRP
Strap (See Table 3-
4 on page 44.)
D7 V
SS
GND --- --- ---
D8 FRAME# I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
---
D9 IOR# O O
3/5
V
IO
PMR[21] = 0 and
PMR[2] = 0
DOCR# O O
3/5
PMR[21] = 0 and
PMR[2] = 1
GPIO14 I/O
(PU
22.5
)
IN
TS
,
O
3/5
PMR[21] = 1 and
PMR[2] = 1
D10 GPIO1 I/O
(PU
22.5
)
IN
T
, O
3/5
V
IO
(PMR[23]
3
= 0 and
PMR[13] = 0) or
(PMR[23]
3
= 1 and
PMR[15] = 1 and
PMR[13] = 0)
IOCS1# O
(PU
22.5
)
O
3/5
V
IO
(PMR[23]
3
= 0 and
PMR[13] = 1) or
(PMR[23]
3
= 1 and
PMR[15] = 1 and
PMR[13] = 1)
TFTD12 O
(PU
22.5
)
O
1/4
V
IO
PMR[23]
3
= 1 and
PMR[15] = 0
Ball
No. Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail Configuration
D11 TRDE# O O
3/5
V
IO
PMR[12] = 0
GPIO0 I/O
(PU
22.5
)
IN
TS
,
O
3/5
V
IO
PMR[12] = 1
D12 V
CCCRT
PWR --- --- ---
D13 V
SS
GND --- --- ---
D14 V
IO
PWR --- --- ---
D15 AV
CCCRT
PWR --- --- ---
D16 VREF I/O WIRE AV
C-
CCRT
---
D17
6, 2
PE I
(PU
22.5
PD
22.5
)
IN
T
V
IO
PMR[23]
3
= 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PU/PD under soft-
ware control.)
TFTD14 O O
1/4
PMR[23]
3
= 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
F_C/BE2# O O
1/4
PMR[23]
3
= 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
D18 V
IO
PWR --- --- ---
D19 V
SS
GND --- --- ---
D20
6,
2
PD2 I/O IN
T
,
O
14/14
V
IO
PMR[23]
3
= 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
TFTD8 O O
1/4
(PMR[23]
3
= 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
VOPD7 O O
1/4
(PMR[23]
3
= 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
F_AD2 O O
14/14
PMR[23]
3
= 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
D21
6, 2
ERR# I IN
T
, O
1/4
V
IO
PMR[23]
3
= 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
TFTD4 O O
1/4
(PMR[23]
3
= 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
VOPD3 O O
1/4
(PMR[23]
3
= 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
F_C/BE0# O O
1/4
PMR[23]
3
= 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
Ball
No. Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail Configuration
Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)