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AMD Geode™ SC1200/SC1201 Processor Data Book 395
Electrical Specifications
32579B
t
RDYA2
IOCHRDY valid after IOR#/MEMR#/
RD#/DOCR#/IOW#/MEMW#/WR#/
DOCW# FE
8 M, I/O 366 9-20
9-21
t
IOCSA
IOCS[1:0]#/DOCS#/ROMCS# driven
active from A[23:0] valid
8, 16 M, I/O 34 9-20
9-21
t
IOCSH
IOCS[1:0]#/DOCS#/ROMCS# valid
hold after A[23:0] invalid
8, 16 M, I/O 0 9-20
9-21
t
AR1
A[23:0]/BHE# valid before
MEMR#/DOCR# active
16 M 34 9-20
t
AR2
A[23:0]/BHE# valid before IOR#
active
16 I/O 100 9-20
t
AR3
A[23:0]/BHE# valid before
MEMR#/DOCR#/IOR# active
8 M, I/O 100 9-20
t
RA
A[23:0]/BHE# valid hold after
MEMR#/DOCR#/IOR# inactive
8, 16 M, I/O 25 9-20
t
RVDS
Read data D[15:0] valid setup before
MEMR#/DOCR#/IOR# inactive
8, 16 M, I/O 24 9-20
t
RDH
Read data D[15:0] valid hold after
MEMR#/DOCR#/IOR# inactive
8, 16 M, I/O 0 9-20
t
HZ
Read data floating after
MEMR#/DOCR#/IOR# inactive
8, 16 M, I/O 41 9-20
t
AW1
A[23:0]/BHE# valid before
MEMW#/DOCW# active
16 M 34 9-21
t
AW2
A[23:0]/BHE# valid before IOW#
active
16 I/O 100 9-21
t
AW3
A[23:0]/BHE# valid before
MEMW#/DOCW#/IOW# active
8 M, I/O 100 9-21
t
WA
A[23:0]/BHE# valid hold after
MEMW#/DOCW#/IOW# invalid
8, 16 M, I/O 25 9-21
t
DV1
Write data D[15:0] valid after
MEMW#/DOCW# active
8, 16 M 40 9-21
t
DV2
Write data D[15:0] valid after IOW#
active
8 I/O 40 9-21
t
DV3
Write data D[15:0] valid after IOW#
active
16 I/O -23 9-21
t
WTR
TRDE# inactive after
MEMW#/DOCW#/IOW# inactive
8, 16 M, I/O 20 9-21
t
DH
Write data D[15:0] after
MEMW#/DOCW#/IOW# inactive
8, 16 M, I/O 45 9-21
t
DF
Write data D[15:0] goes TRI-STATE
after MEMW#/DOCW#/IOW# inactive
8, 16 M, I/O 105 9-21
t
WDAR
Write data D[15:0] after read
MEMR#/DOCR#/IOR#
8, 16 M, I/O 41 9-20
Table 9-24. Sub-ISA Timing Parameters (Continued)
Symbol Parameter
Bus
Width
(Bits) Type
Min
(ns)
Max
(ns) Figure Comments