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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ............. 53
5.1 Pipeline Operation ............................................................................................................................ 54
5.2 Pipeline Operation and Interrupt Processing .................................................................................... 55
5.3 Register Hazards .............................................................................................................................. 56
5.4 Delayed Branching Processing ......................................................................................................... 58
5.4.1 Processing Non-delayed Branching Instructions ......................................................................... 60
5.4.2 Processing Delayed Branching Instructions ................................................................................ 61
CHAPTER 6 INSTRUCTION OVERVIEW ....................................................................... 63
6.1 Instruction Formats ........................................................................................................................... 64
6.2 Instruction Notation Formats ............................................................................................................. 66
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ................................................ 67
7.1 ADD (Add Word Data of Source Register to Destination Register) .................................................. 72
7.2 ADD (Add 4-bit Immediate Data to Destination Register) ................................................................. 73
7.3 ADD2 (Add 4-bit Immediate Data to Destination Register) ............................................................... 74
7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) ......................... 75
7.5 ADDN (Add Word Data of Source Register to Destination Register) ............................................... 76
7.6 ADDN (Add Immediate Data to Destination Register) ...................................................................... 77
7.7 ADDN2 (Add Immediate Data to Destination Register) .................................................................... 78
7.8 SUB (Subtract Word Data in Source Register from Destination Register) ....................................... 79
7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) ............... 80
7.10 SUBN (Subtract Word Data in Source Register from Destination Register) ..................................... 81
7.11 CMP (Compare Word Data in Source Register and Destination Register) ...................................... 82
7.12 CMP (Compare Immediate Data of Source Register and Destination Register) .............................. 83
7.13 CMP2 (Compare Immediate Data and Destination Register) ........................................................... 84
7.14 AND (And Word Data of Source Register to Destination Register) .................................................. 85
7.15 AND (And Word Data of Source Register to Data in Memory) ......................................................... 86
7.16 ANDH (And Half-word Data of Source Register to Data in Memory) ................................................ 88
7.17 ANDB (And Byte Data of Source Register to Data in Memory) ........................................................ 90
7.18 OR (Or Word Data of Source Register to Destination Register) ....................................................... 92
7.19 OR (Or Word Data of Source Register to Data in Memory) .............................................................. 93
7.20 ORH (Or Half-word Data of Source Register to Data in Memory) .................................................... 95
7.21 ORB (Or Byte Data of Source Register to Data in Memory) ............................................................. 97
7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register) .................................... 99
7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory) ......................................... 100
7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory) ................................ 102
7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory) ........................................ 104
7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ................................ 106
7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) ............................... 108
7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ..................................... 110
7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) ................................... 112
7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ................................. 114
7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) ............................... 116
7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory) ....................................................................... 118
7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory) ..................................................................... 119
7.34 MUL (Multiply Word Data) .............................................................................................................. 120