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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.129 LDM0 (Load Multiple Registers)
The "LDM0" instruction accepts registers in the range R0 to R7 as members of the
parameter "reglist". (See Table 7.129-1.)
Registers are processed in ascending numerical order.
■ LDM0 (Load Multiple Registers)
Assembler format: LDM0 (reglist)
Operation: The following operations are repeated according to the number of registers specified in the
parameter "reglist".
(R15) → Ri
R15 + 4 → R15
Flag change:
N, Z, V, and C: Unchanged
Execution cycles: If "n" is the number of registers specified in the parameter "reglist", the execution cycles
required are as follows.
If n=0: 1 cycle
For other values of n: a (n – 1) + b + 1 cycles
Instruction format:
NZVC
––––
Table 7.129-1 Bit Values and Register Numbers for "reglist" (LDM0)
Bit Register Bit Register
7R73R3
6R62R2
5R51R1
4R40R0
MSB LSB
10001100
reglist