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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
5.4 Delayed Branching Processing
Because the FR family CPU features pipeline operation, branching instructions must
first be loaded before they are executed. Delayed branching processing is the function
to execute the loaded instruction, and allows to accelerate processing speeds.
■ Overview of Branching with Non-delayed Branching Instructions
In a pipeline operation, by the time the CPU recognizes an instruction as a branching instruction the next
instruction has already been loaded. To process the program as written, the instruction following the
branching instruction must be canceled in the middle of execution. Branching instructions that are handled
in this manner are non-delayed branching instructions.
Examples of processing non-delayed branching instructions (both when branching conditions are satisfied
and not satisfied) are described in Section "5.4.1 Processing Non-delayed Branching Instructions".
■ Overview of Branching with Delayed Branching Instructions
An instruction immediately following a branching instruction will already be loaded by the CPU by the
time the branching instruction is executed. This position is called the delay slot.
A delayed branching instruction is a branching instruction that executes the instruction in the delay slot
regardless of whether the branching conditions are satisfied or not satisfied.
Examples of processing delayed branching instructions (both when branching conditions are satisfied and
not satisfied) are described in Section "5.4.2 Processing Delayed Branching Instructions".
■ Instructions Prohibited in Delay Slots
The following instructions may not be used in delayed branching processing by the FR family CPU.
• LDI:32 #i32, Ri LDI:20 #i20, Ri
• COPOP #u4, #CC, CRj, CRi
COPLD #u4, #CC, Rj, CRi
COPST #u4, #CC, CRj, Ri
COPSV #u4, #CC, CRj, Ri
• JMP @Ri
CALL label12
CALL @Ri
RET
Conditional branching instruction and related delayed branching instructions
• INT #u8
RETI
INTE