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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.50 ASR (Arithmetic Shift to the Right Direction)
Makes an arithmetic right shift of the word data in "Ri" by "Rj" bits, stores the result to
"Ri".
Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the
shift range is 0 to 31 bits.
■ ASR (Arithmetic Shift to the Right Direction)
Assembler format: ASR Rj, Ri
Operation: Ri >> Rj → Ri
Flag change:
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
Execution cycles: 1 cycle
Instruction format:
Example: ASR R2, R3
NZVC
CC–C
MSB LSB
10111010 Rj Ri
R2
R3
R2
R3
FFFF 0FFF
0000 0008
FF0F FFFF
0000 0008
NZVC
CCR CCR
NZVC
10010000
Before execution After execution
Instruction bit pattern : 1011 1010 0010 0011