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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.18 OR (Or Word Data of Source Register to Destination
Register)
Takes the logical OR of the word data in "Ri" and the word data in "Rj", stores the
results to "Ri".
■ OR (Or Word Data of Source Register to Destination Register)
Assembler format: OR Rj, Ri
Operation: Ri or Rj → Ri
Flag change:
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles: 1 cycle
Instruction format:
Example: OR R2, R3
NZVC
CC– –
MSB LSB
10010010 Rj Ri
R2
R3
1111 0000
1010 1010
NZVC
CCR
R2
R3
CCR
0000
NZVC
0000
1111 1010
1111 0000
Before execution After execution
Instruction bit pattern : 1001 0010 0010 0011