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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.14 AND (And Word Data of Source Register to Destination
Register)
Takes the logical AND of the word data in "Rj" and the word data in "Ri", stores the
results to "Ri".
■ AND (And Word Data of Source Register to Destination Register)
Assembler format: AND Rj, Ri
Operation: Ri and Rj → Ri
Flag change:
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles: 1 cycle
Instruction format:
Example: AND R2, R3
NZVC
CC– –
MSB LSB
10000010 Rj Ri
R2
R3
1111 0000
1010 1010
NZVC
CCR
R2
R3
CCR
0000
NZVC
0000
1010 0000
1111 0000
Before execution After execution
Instruction bit pattern : 1000 0010 0010 0011