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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.132 STM1 (Store Multiple Registers)
The "STM1" instruction accepts registers in the range R8 to R15 as members of the
parameter "reglist" (See Table 7.132-1.).
Registers are processed in descending numerical order.
If "R15" is specified in the parameter "reglist", the contents of "R15" retained before the
instruction is executed will be written to memory.
■ STM1 (Store Multiple Registers)
Assembler format: STM1 (reglist)
Operation: The following operations are repeated according to the number of registers specified in the
parameter "reglist".
R15 – 4 → R15
Ri → (R15)
Flag change:
N, Z, V, and C: Unchanged
Execution cycles: If "n" is the number of registers specified in the parameter "reglist", the execution cycles
required are as follows.
a × n + 1 cycles
Instruction format:
NZVC
––––
Table 7.132-1 Bit Values and Register Numbers for "reglist" (STM1)
Bit Register Bit Register
7R83R12
6R92R13
5R101R14
4R110R15
MSB LSB
10001111
reglist