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CHAPTER 1 FR FAMILY OVERVIEW
1.3 Sample Configuration of the FR Family CPU
The FR family CPU core features a block configuration organized around general-
purpose registers, with dedicated registers, "ALU" units, multipliers and other features
included for each specific application.
Figure 1.3-1 shows a sample configuration of an FR family CPU.
■ Sample Configuration of the FR Family CPU
Figure 1.3-1 Sample Configuration of the FR Family CPU
Instruction
data
Instruction
sequencer
Instruction
decoder
Bypass
interlock
Wait cancel
control
Exception
processing
Interrupt
NMI
Wait bus
control
Internal bus
Internal bus
Internal bus
Data
Data address
Instruction
address
Multiplier
32 x 8
bits
ALU
Barrel
shifter
Bypass
Register
file
PC
adder
/inc
PC
Pipeline
control