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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
•AND Rj, @Ri
ANDH Rj, @Ri
ANDB Rj, @Ri
OR Rj, @Ri
ORH Rj, @Ri
ORB Rj, @Ri
EOR Rj, @Ri
EORH Rj, @Ri
EORB Rj, @Ri
• BANDH #u4, @Ri
BANDL #u4, @Ri
BORH #u4, @Ri
BORL #u4, @Ri
BEORH #u4, @Ri
BEORL #u4, @Ri
BTSTH #u4, @Ri
BTSTL #u4, @Ri
• MUL Rj, Ri
MULU Rj, Ri
MULH Rj, Ri
MULUH Rj, Ri
•LD @R15+, PS
• LDM0 (reglist)
LDM1 (reglist)
STM0 (reglist)
STM1 (reglist)
ENTER #u10
XCHB @Rj, Ri
• DMOV @dir10, @R13+
DMOV @R13+, @dir10
DMOV @dir10, @-R15
DMOV @R15+, @dir10
DMOVH @dir9, @R13+
DMOVH @R13+, @dir9
DMOVB @dir8, @R13+
DMOVB @R13+, @dir8
■ Restrictions on Interrupts during Processing of Delayed Branching Instructions
"EIT" processing is not accepted during execution of delayed branching instructions or delayed branching
processing.