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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.40 DIV1 (Main Process of Division)
7.41 DIV2 (Correction when Remainder is 0)
7.42 DIV3 (Correction when Remainder is 0)
7.43 DIV4S (Correction Answer for Signed Division)
7.44 LSL (Logical Shift to the Left Direction)
7.45 LSL (Logical Shift to the Left Direction)
7.46 LSL2 (Logical Shift to the Left Direction)
7.47 LSR (Logical Shift to the Right Direction)
7.48 LSR (Logical Shift to the Right Direction)
7.49 LSR2 (Logical Shift to the Right Direction)
7.50 ASR (Arithmetic Shift to the Right Direction)
7.51 ASR (Arithmetic Shift to the Right Direction)
7.52 ASR2 (Arithmetic Shift to the Right Direction)
7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register)
7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register)
7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register)
7.56 LD (Load Word Data in Memory to Register)
7.57 LD (Load Word Data in Memory to Register)
7.58 LD (Load Word Data in Memory to Register)
7.59 LD (Load Word Data in Memory to Register)
7.60 LD (Load Word Data in Memory to Register)
7.61 LD (Load Word Data in Memory to Register)
7.62 LD (Load Word Data in Memory to Program Status Register)
7.63 LDUH (Load Half-word Data in Memory to Register)
7.64 LDUH (Load Half-word Data in Memory to Register)
7.65 LDUH (Load Half-word Data in Memory to Register)
7.66 LDUB (Load Byte Data in Memory to Register)
7.67 LDUB (Load Byte Data in Memory to Register)
7.68 LDUB (Load Byte Data in Memory to Register)
7.69 ST (Store Word Data in Register to Memory)
7.70 ST (Store Word Data in Register to Memory)
7.71 ST (Store Word Data in Register to Memory)
7.72 ST (Store Word Data in Register to Memory)
7.73 ST (Store Word Data in Register to Memory)
7.74 ST (Store Word Data in Register to Memory)
7.75 ST (Store Word Data in Program Status Register to Memory)
7.76 STH (Store Half-word Data in Register to Memory)