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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.1 ADD (Add Word Data of Source Register to Destination
Register)
Adds word data in "Rj" to word data in "Ri", stores results to "Ri".
■ ADD (Add Word Data of Source Register to Destination Register)
Assembler format: ADD Rj, Ri
Operation: Ri + Rj → Ri
Flag change:
N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a carry has occurred as a result of the operation, cleared otherwise.
Execution cycles: 1 cycle
Instruction format:
Example: ADD R2, R3
NZVC
CCCC
MSB LSB
10100110 Rj Ri
R2
R3
123 4 5678
8 765 43 21
NZVC
CCR
R2
R3
CCR
0000
NZVC
1000
9999 9999
123 4 5678
Before execution After execution
Instruction bit pattern : 1010 0110 0010 0011