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38
"4.3.1 User Interrupts" is changed.
( "External" → "User" ), ( "external" → "user" )
"■ Overview of User Interrupts" is changed.
( "External" → "User" )
"■ Overview of User Interrupts" is changed.
( "Interrupts are referred to as "external" when they originate outside the CPU." is deleted. )
"■ Conditions for Acceptance of User Interrupt Requests" is changed.
( "External" → "User" )
"■ Conditions for Acceptance of User Interrupt Requests" is changed.
( "The CPU accepts interrupts" → "The CPU accepts user interrupts" )
"■ Operation Following Acceptance of an User Interrupt" is changed.
( "External" → "User" ), ( "external" → "user" )
39
"■ How to Use User Interrupts" is changed.
( "External" → "User" ), ( "external" → "user" )
"Figure 4.3-1 How to Use User Interrupts" is changed.
( "External" → "User" )
51
"Table 4.6-1 Priority of "EIT" Requests" is changed.
( "External" → "User"), ("INT" → "INTE")
62
"■ Examples of Programing Delayed Branching Instructions" is changed.
( The position of comment ";not satisfy" is changed. )
( R12 → R13)
66
"● Calculations are designated by a mnemonic placed between operand 1 and operand 2, with the results
stored at operand 2" is changed.
( The position of R2 is changed. )
72
"7.1 ADD (Add Word Data of Source Register to Destination Register)" is changed.
( "Instruction bit pattern : 1010 0110 0010 0011" is added. )
75
"7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)" is changed.
( "Instruction bit pattern : 1010 0111 0010 0011" is added. )
79
"7.8 SUB (Subtract Word Data in Source Register from Destination Register)" is changed.
( "Instruction bit pattern : 1010 1100 0010 0011" is added. )
80
"7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)" is changed.
( "Instruction bit pattern : 1010 1101 0010 0011" is added. )
81
"7.10 SUBN (Subtract Word Data in Source Register from Destination Register)" is changed.
( "Instruction bit pattern : 1010 1110 0010 0011" is added. )
82
"7.11 CMP (Compare Word Data in Source Register and Destination Register)" is changed.
( "Instruction bit pattern : 1010 1010 0010 0011" is added. )
85
"7.14 AND (And Word Data of Source Register to Destination Register)" is changed.
( "Instruction bit pattern : 1000 0010 0010 0011" is added. )
Page Changes (For details, refer to main body.)