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CHAPTER 1 FR FAMILY OVERVIEW
1.1 Features of the FR Family CPU Core
The FR family CPU core features proprietary Fujitsu architecture and is designed for
controller applications using 32-bit "RISC" based computing. The architecture is
optimized for use in microcontroller CPU cores for built-in control applications where
high-speed control is required.
■ Features of the FR Family CPU Core
• General-purpose register architecture
• Linear space for 32-bit (4 Gbytes) addressing
• 16-bit fixed instruction length (excluding immediate data, coprocessor instructions)
• 5-stage pipeline configuration for basic instructions, one-instruction one-cycle execution
• 32-bit by 32-bit computation enables completion of multiplication instructions within five cycles
• Stepwise division instructions enable 32-bit/ 32-bit division
• Direct addressing instructions for peripheral circuit access
• Coprocessor instructions for direct designation of peripheral accelerator
• High speed interrupt processing complete within 6 cycles