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87
"7.15 AND (And Word Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1000 0100 0010 0011" is added.)
89
"7.16 ANDH (And Half-word Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1000 0101 0010 0011" is added. )
91
"7.17 ANDB (And Byte Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1000 0110 0010 0011" is added. )
92
"7.18 OR (Or Word Data of Source Register to Destination Register)" is changed.
( "Instruction bit pattern : 1001 0010 0010 0011" is added.)
94
"7.19 OR (Or Word Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1001 0100 0010 0011" is added. )
96
"7.20 ORH (Or Half-word Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1001 0101 0010 0011" is added. )
98
"7.21 ORB (Or Byte Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1001 0110 0010 0011" is added. )
99
"7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register)" is changed.
( "Instruction bit pattern : 1001 1010 0010 0011" is added. )
101
"7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1001 1100 0010 0011" is added. )
103
"7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1001 1101 0010 0011" is added. )
105
"7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1001 1110 0010 0011" is added. )
121
"7.34 MUL (Multiply Word Data)" is changed.
( "Instruction bit pattern : 1010 1111 0010 0011" is added. )
123
"7.35 MULU (Multiply Unsigned Word Data)" is changed.
( "Instruction bit pattern : 1010 1011 0010 0011" is added. )
125
"7.36 MULH (Multiply Half-word Data)" is changed.
( "Instruction bit pattern : 1011 1111 0010 0011" is added. )
127
"7.37 MULUH (Multiply Unsigned Half-word Data)" is changed.
( "Instruction bit pattern : 1011 1011 0010 0011" is added. )
129
"7.38 DIV0S (Initial Setting Up for Signed Division)" is changed.
( "Instruction bit pattern : 1001 0111 0100 0010" is added. )
131
"7.39 DIV0U (Initial Setting Up for Unsigned Division)147/308" is changed.
( "Instruction bit pattern : 1001 0111 0101 0010" is added. )
133
"7.40 DIV1 (Main Process of Division)" is changed.
( "Instruction bit pattern : 1001 0111 0110 0010" is added. )
135
"7.41 DIV2 (Correction when Remainder is 0)" is changed.
( "Instruction bit pattern : 1001 0111 0111 0010" is added. )
Page Changes (For details, refer to main body.)