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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.3 ADD2 (Add 4-bit Immediate Data to Destination Register)
Adds the result of the higher 28 bits of 4-bit immediate data with minus extension to the
word data in "Ri", stores results to "Ri".
The way a "C" flag of this instruction varies is the same as the ADD instruction ; it is
different from that of the SUB instruction.
■ ADD2 (Add 4-bit Immediate Data to Destination Register)
Assembler format: ADD2 #i4, Ri
Operation: Ri + extn(i4) → Ri
Flag change:
N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a carry has occurred as a result of the operation, cleared otherwise.
Execution cycles: 1 cycle
Instruction format:
Example: ADD2 #–2, R3
NZVC
CCCC
MSB LSB
10100101 i4 Ri
R3
9999 9999
NZVC
CCR
R3
CCR
0000
NZVC
1001
9999 9997
Instruction bit pattern : 1010 0101 1110 0011
Before execution After execution