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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
5.3 Register Hazards
The FR family CPU executes program steps in the order in which they are written, and is
therefore equipped with a function that detects the occurrence of register hazards and
stops pipeline processing when necessary. This enables programs to be written without
attention to the order in which registers are used
■ Overview of Register Hazards
The CPU in pipeline operation may simultaneously process one instruction that involves writing values to a
register, and a subsequent instruction that attempts to refer to the same register before the write process is
completed. This is called a register hazard.
In the example in Figure 5.3-1, the program will read the address value at "R1" before the desired value has
been written to "R1" by the previous instruction. As a result, the old value at "R1" will be read instead of
the new value.
Figure 5.3-1 Example of a Register Hazard
■ Register Bypassing
Even when a register hazard does occur, it is possible to process instructions without operating delays if the
data intended for the register to be accessed can be extricated from the preceding instruction. This type of
data transfer processing is called register bypassing, and the FR family CPU is equipped with a register
bypass function.
In the example in Figure 5.3-2, instead of reading the "R1" in the "ID" stage of the "SUB" instruction, the
program uses the results of the calculation from the "EX" stage of the "ADD" instruction (before the results
are written to the register) and thus executes the instruction without delay.
Figure 5.3-2 Example of a Register Bypass
IF ID EX MA WB : Write cycle to R1
: Read cycle from R1
IF ID EX MA WBSUB R1, R2
ADD R0, R1
IF ID EX MA WB : Data calculation cycle to R1
: Read cycle from R1
IF ID EX MA WBSUB R1, R2
ADD R0, R1