Fujitsu CM71-00101-5E Server User Manual


 
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CHAPTER 3 REGISTER DESCRIPTIONS
Table Base Register Configuration
Figure 3.3-8 shows the bit configuration of the table base register.
Figure 3.3-8 Table Base Register Bit Configuration
Table Base Register Functions
Vector Table Reference Addresses
Addresses for vector reference are generated by adding the contents of the "TBR" register and the vector
offset value, which is determined by the type of interrupt used. Because vector access is in word units, the
lower two bits of the resulting address value are explicitly read as "0".
Vector Table Layout
Vector table layout can be realized in word (32 bits) units.
Initial Values in Table Base Register
After a reset, the initial value is "000FFC00
H
".
Precautions Related to the Table Base Register
The "TBR" should not be assigned values greater than "FFFFFC00
H
". If values higher than this are placed
in the register, the operation may result in an overflow when summed with the offset value. An overflow
condition will result in vector access to the area "00000000
H
" to "000003FF
H
", which can cause program
runaway.
Bit no.
TBR
31
00