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CHAPTER 2 NDA-24296
Page 134
Revision 1.0
PU-SW00/PU-SW00-A
Time Division Switch
PU-SW00/PU-SW00-A
Time Division Switch
1. General Function
The PU-SW00/PU-SW00-A circuit card provides the Time division Switch (TSW) and INT function for
the IPX-U/IPX-UMG system. Each circuit card provides switching for a Local Node (LN) and four PU-
SW00/PU-SW00-A cards and two PU-SW01 (HSW) cards achieve a maximum of 32,768 time slot (TS)
switching for four (4) LNs/LMGs. This circuit card is located in ISWM of the ISW/CMG.
Figure 2-62 Location of PU-SW00/PU-SW00-A (TSW)
MUX00
LC/TRK
LC/TRK
LC/TRK
LC/TRK
DLKC0
LC/TRK
LC/TRK
LC/TRK
LC/TRK
LC/TRK
LC/TRK
LC/TRK
LC/TRK
LC/TRK
LC/TRK
LC/TRK
LC/TRK
MUX01
MUX02
MUX03
MUX10
MUX11
MUX12
MUX13
TSW00
TSW10
TSW01
TSW11
TSW02
TSW12
TSW03
TSW13
PLO 0
PLO 0
DLKC1
PLO 1
PLO 1
MUX
MUX
TSW00
TSW01
TSW02
TSW03
HSW00
HSW01
HSW10
HSW11
TSW10
TSW11
TSW12
TSW13
[TSW Configuration]
2M PCM HW x8
2M PCM HW x8
2M PCM HW x8
2M PCM HW x8
2M PCM HW x8
2M PCM HW x8
2M PCM HW x8
2M PCM HW x8
32M TSW
Matrix HW
32M SERIAL HW
32M SERIAL HW
x4
32M SERIAL HW
x4
32M SERIAL HW
x4
32M SERIAL HW
x4
64KHz
Clock
64KHz
Clock
32M TSW
Matrix HW
32.768MHz Clock
DCS
32.768MHz Clock
DCS
32.768MHz Clock
32.768MHz Clock