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PRODUCT PREVIEW
1TMS320C6454Fixed-PointDigitalSignalProcessor
1.1Features
TMS320C6454
Fixed-PointDigitalSignalProcessor
SPRS311A–APRIL2006–REVISEDDECEMBER2006
•32-BitDDR2MemoryController(DDR2-533
•High-PerformanceFixed-PointDSP(C6454)
SDRAM)
–1.39-,1.17-,and1-nsInstructionCycleTime
•EDMA3Controller(64IndependentChannels)
–720-MHz,850-MHz,and1-GHzClockRate
–Eight32-BitInstructions/Cycle
•32-/16-BitHost-PortInterface(HPI)
–8000MIPS/MMACS(16-Bits)
•32-Bit33-/66-MHz,3.3-VPeripheralComponent
–CommercialTemperature[0°Cto90°C]
Interconnect(PCI)Master/SlaveInterface
ConformstoPCISpecification2.3
•TMS320C64x+™DSPCore
–DedicatedSPLOOPInstruction
•OneInter-IntegratedCircuit(I
2
C)Bus
–CompactInstructions(16-Bit)
•TwoMcBSPs
–InstructionSetEnhancements
•10/100/1000Mb/sEthernetMAC(EMAC)
–ExceptionHandling
–IEEE802.3Compliant
•TMS320C64x+MegamoduleL1/L2Memory
–SupportsMultipleMediaIndependent
Architecture:
Interfaces(MII,GMII,RMII,andRGMII)
–256K-Bit(32K-Byte)L1PProgramCache
–8IndependentTransmit(TX)and
[DirectMapped]
8IndependentReceive(RX)Channels
–256K-Bit(32K-Byte)L1DDataCache
•Two64-BitGeneral-PurposeTimers,
[2-WaySet-Associative]
ConfigurableasFour32-BitTimers
–8M-Bit(1048K-Byte)L2UnifiedMapped
•16General-PurposeI/O(GPIO)Pins
RAM/Cache[FlexibleAllocation]
•SystemPLLandPLLController
–256K-Bit(32K-Byte)L2ROM
•SecondaryPLLandPLLController,Dedicated
–TimeStampCounter
toEMACandDDR2MemoryController
•Endianess:LittleEndian,BigEndian
•IEEE-1149.1(JTAG™)
•64-BitExternalMemoryInterface(EMIFA)
Boundary-Scan-Compatible
–GluelessInterfacetoAsynchronous
•697-PinBallGridArray(BGA)Package
Memories(SRAM,Flash,andEEPROM)and
(ZTZorGTZSuffix),0.8-mmBallPitch
SynchronousMemories(SBSRAMandZBT
SRAM)
•0.09-µm/7-LevelCuMetalProcess(CMOS)
–SupportsInterfacetoStandardSync
•3.3-/1.8-/1.5-VI/Os,1.25-/1.2-VInternal
DevicesandCustomLogic(FPGA,CPLD,
•Pin-CompatiblewiththeTMS320C6455
ASICs,etc.)
Fixed-PointDigitalSignalProcessor
–32M-ByteTotalAddressableExternal
MemorySpace
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