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TMS320C6454
Fixed-PointDigitalSignalProcessor
SPRS311A–APRIL2006–REVISEDDECEMBER2006
C6454RevisionHistory(continued)
SEEADDITIONS/MODIFICATIONS/DELETIONS
Section7.7.3PLL1ControllerRegisterDescriptions:
AddedValuesandDescriptionsforRATIObitfieldinTable7-21,PLLPre-DividerControlRegister(PREDIV)
FieldDescriptions
DeletedPLLControllerDividerRegisterssection
AddednewsectionsforPLLControllerDivider4RegisterandPLLControllerDivider5Register
ChangeRATIObitfieldresettoR/W-3inFigure7-14,PLLControllerDivider4Register(PLLDIV4)
ChangedRATIObitfieldresettoR/W-3inFigure7-15,PLLControllerDivider5Register(PLLDIV5)
Section7.7.4PLL1ControllerInputandOutputClockElectricalData/Timing:
UpdatedFigure7-22,SYSCLK4Timing
Section7.8PLL2andPLL2Controller:
UpdatedNotesAandBonFigure7-23,PLL2BlockDiagram
Section7.8.1PLL2ControllerDevice-SpecificInformation:
UpdatedFootnote(1)inTable7-31,PLL2ClockFrequencyRanges
Section7.8.1.1InternalClocksandMaximumOperatingFrequencies:
Updatedparagraphs
Section7.8.4PLL2ControllerInputClockElectricalData/Timing:
UpdatedFootnote(3)inTable7-39,TimingRequirementsforCLKIN2
Section7.9DDR2MemoryController:
Updatedparagraphs
Section7.10.2EMIFAPeripheralRegisterDescription(s):
ChangedBurstPriorityRegisteracronymtoBURST_PRIOinTable7-41,EMIFARegisters
Section7.10.3EMIFAElectricalData/Timing:
UpdatedfootnotesforTable7-45,Table7-47andFigure7-33,Figure7-36,Figure7-37,andFigure7-38
UpdatedFigure7-34,AsynchronousMemoryWriteTimingforEMIFA
Section7.12.2HPIPeripheralRegisterDescription(s):
UpdatedCommentsforHPICinTable7-54,HPIControlRegisters
UpdatedHexAddressandCommentsforHPIAregisters
AddedFootnote(1)
UpdatedFootnote(2)
Section7.12.3HPIElectricalData/Timing:
ChangedParameterNO.18MINvalueto1nsandParameterNO.38MINvalueto1.1nsinTable7-55,
TimingRequirementsforHost-PortInterfaceCycles
ReplacedTBDdocumentreferencewithTMS320C645xDSPHostPortInterfaceUser'sGuide(literature
numberSPRU969)inFigure7-44throughFigure7-51
Section7.13.1McBSPDevice-SpecificInformation:
Addedparagraph
Section7.13.2McBSPElectricalData/Timing:
ChangedParameterNO.4MAXvalueto3.3nsinTable7-60,SwitchingCharacteristicsOver
RecommendedOperatingConditionsforMcBSP
Section7.14.1EMACDevice-SpecificInformation:
DeletedStep1andchangedsettingtoclearingunderUsingtheRMIIModeoftheEMAC
MovedTable7-70,EMAC/MDIOMultiplexedPins(MII,RMII,andGMIIModes),underInterfaceModeSelect
AddedInterfaceModeClockingsectionandparagraphs
Section7.14.2EMACPeripheralRegisterDescription(s):
CorrectedHexAddressesfor02C80080through02C80090inTable7-71,EthernetMAC(EMAC)Control
Registers
Section7.14.3.1EMACMIIandGMIIElectricalData/Timing:
UpdatedFigure7-59,MRCLKTiming(EMAC–Receive)[MIIandGMIIOperation]
UpdatedFigure7-60,MTCLKTiming(EMAC–Transmit)[MIIandGMIIOperation]
ChangedTable7-77titletoSwitchingCharacteristicsOverRecommendedOperatingConditionsfor
GMTCLK-GMIIOperation
UpdatedFigure7-61,GMTCLKTiming(EMAC–Transmit)[GMIIOperation]
UpdatedFigure7-64,EMACTransmitInterfaceTiming[GMIIOperation]
Section7.14.3.2EMACRMIIElectricalData/Timing:
Addedthefollowingtablesandfigures:
Table7-82,SwitchingCharacteristicsOverRecommendedOperatingConditionsforEMACRMIITransmit
10/100Mbit/s
Figure7-66,EMACTransmitInterfaceTiming[RMIIOperation]
Table7-83,TimingRequirementsforEMACRMIIInputReceivefor100Mbps
Figure7-67,EMACReceiveInterfaceTiming[RMIIOperation]
RevisionHistory 220SubmitDocumentationFeedback