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7.16PeripheralComponentInterconnect(PCI)
7.16.1PCIDevice-SpecificInformation
TMS320C6454
Fixed-PointDigitalSignalProcessor
SPRS311A–APRIL2006–REVISEDDECEMBER2006
TheC6454DSPsupportsconnectionstoaPCIbackplaneviatheintegratedPCImaster/slavebus
interface.ThePCIportinterfacestoDSPinternalresourcesviathedataswitchedcentralresource.The
dataswitchedcentralresourceisdescribedinmoredetailinSection4.
FormoredetailedinformationonthePCIportperipheralmodule,seetheTMS320C645xDSPPeripheral
ComponentInterconnect(PCI)User'sGuide(literaturenumberSPRUE60).
ThePCIperipheralontheC6454DSPconformstothePCILocalBusSpecification(version2.3).ThePCI
peripheralcanactbothasaPCIbusmasterandasatarget.ItsupportsPCIbusoperationofspeedsup
to66MHzandusesa32-bitdata/addressbus.
OntheC6454device,thepinsofthePCIperipheralaremultiplexedwiththepinsoftheHPIandGPIO
peripherals.PCIfunctionalityforthesepinsiscontrolled(enabled/disabled)bythePCI_ENpin(Y29).The
maximumspeedofthePCI,33MHzor66MHz,iscontrolledthroughthePCI66pin(U27).Formore
detailedinformationontheperipheralcontrol,seeSection3,DeviceConfiguration.
TheC6454deviceprovidesaninitializationmechanismthroughwhichthedefaultvaluesforsomeofthe
PCIconfigurationregisterscanbereadfromanI2CEEPROM.Table7-96showstheregisterswhichcan
beinitializedthroughthePCIauto-initialization.Alsoshownisthedefaultvalueoftheseregisterswhen
PCIauto-initializationisnotused.PCIauto-initializationiscontrolled(enabled/disabled)throughthe
PCI_EEAIpin(P25).Formoreinformationonthisfeature,seetheTMS320C645xDSPPeripheral
ComponentInterconnect(PCI)User'sGuide(literaturenumberSPRUE60)andtheTMS320C645x
BootloaderUser'sGuide(literaturenumberSPRUEC6).
Table7-96.DefaultValuesforPCIConfiguration
Registers
DEFAULT
REGISTER
VALUE
VendorID/DeviceIDRegister(PCIVENDEV)104CB000h
ClassCode/RevisionIDRegister(PCICLREV)00000001h
SubsystemVendorID/SubsystemIDRegister00000000h
(PCISUBID)
MaxLatency/MinGrant/InterruptPin/InterruptLine00000100h
Register(PCILGINT)
Theon-chipBootloadersupportsahostbootwhichallowsanexternalPCIdevicetoloadapplicationcode
intotheDSP'smemoryspace.ThePCIbootisterminatedwhentheHostgeneratesaDSPinterrupt.The
HostcangenerateaDSPinterruptthroughthePCIperipheralbysettingtheDSPINTbitintheBack-End
ApplicationInterruptEnableSetRegister(PCIBINTSET)andtheStatusSetRegister(PCISTATSET).For
moreinformationonthebootsequenceoftheC6454DSP,seeSection2.4.
NOTE
Afterthehostbootiscomplete,theDSPinterruptisregisteredinbit0(channel0)ofthe
EDMAEventRegister(ER).Thiseventmustbeclearedbysoftwarebeforetriggering
transfersonDMAchannel0.
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