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TMS320C6454
Fixed-PointDigitalSignalProcessor
SPRS311A–APRIL2006–REVISEDDECEMBER2006
InterfaceModeClocking
Theon-chipPLL2andPLL2ControllergeneratealltheclockstotheEMACmodule.Whenenabled,the
inputclocktothePLL2Controller(CLKIN2)musthavea25MHzfrequency.Formoreinformation,see
Section7.8,PLL2andPLL2Controller.
TheEMACusesSYSCLK1ofthePLL2ControllertogeneratethenecessaryclocksfortheGMIIand
RGMIImodes.Whenthesemodesareused,thefrequencyofCLKIN2mustbe25MHz.Also,dividerD1
shouldbeprogrammedto÷2mode[default]whenusingtheGMIImodeandto÷5modewhenusingthe
RGMIImode.DividerD1issoftwareprogrammableand,ifnecessary,mustbeprogrammedafterdevice
resetto÷5whentheRGMIImodeoftheEMACisused.
190C64x+PeripheralInformationandElectricalSpecificationsSubmitDocumentationFeedback