Filter
Top Products
www.ti.com
PRODUCT PREVIEW
2.2CPU(DSPCore)Description
TMS320C6454
Fixed-PointDigitalSignalProcessor
SPRS311A–APRIL2006–REVISEDDECEMBER2006
Table2-1.CharacteristicsoftheC6454Processor(continued)
HARDWAREFEATURESC6454
TMX320C6454ZTZ7,
(FormoredetailsontheC64x+™DSPpart
DevicePartNumbersTMX320C6454ZTZ8,
numbering,seeFigure2-12)
TMX320C6454ZTZ
TheC64x+CentralProcessingUnit(CPU)consistsofeightfunctionalunits,tworegisterfiles,andtwo
datapathsasshowninFigure2-1.Thetwogeneral-purposeregisterfiles(AandB)eachcontain
3232-bitregistersforatotalof64registers.Thegeneral-purposeregisterscanbeusedfordataorcanbe
dataaddresspointers.Thedatatypessupportedincludepacked8-bitdata,packed16-bitdata,32-bit
data,40-bitdata,and64-bitdata.Valueslargerthan32bits,suchas40-bit-longor64-bit-longvaluesare
storedinregisterpairs,withthe32LSBsofdataplacedinanevenregisterandtheremaining8or
32MSBsinthenextupperregister(whichisalwaysanodd-numberedregister).
Theeightfunctionalunits(.M1,.L1,.D1,.S1,.M2,.L2,.D2,and.S2)areeachcapableofexecutingone
instructioneveryclockcycle.The.Mfunctionalunitsperformallmultiplyoperations.The.Sand.Lunits
performageneralsetofarithmetic,logical,andbranchfunctions.The.Dunitsprimarilyloaddatafrom
memorytotheregisterfileandstoreresultsfromtheregisterfileintomemory.
TheC64x+CPUextendstheperformanceoftheC64xcorethroughenhancementsandnewfeatures.
EachC64x+.Munitcanperformoneofthefollowingeachclockcycle:one32x32bitmultiply,two
16x16bitmultiplies,two16x32bitmultiplies,four8x8bitmultiplies,four8x8bitmultiplieswithadd
operations,andfour16x16multiplieswithadd/subtractcapabilities(includingacomplexmultiply).There
isalsosupportforGaloisfieldmultiplicationfor8-bitand32-bitdata.Manycommunicationsalgorithms
suchasFFTsandmodemsrequirecomplexmultiplication.Thecomplexmultiply(CMPY)instructiontakes
for16-bitinputsandproducesa32-bitrealanda32-bitimaginaryoutput.Therearealsocomplex
multiplieswithroundingcapabilitythatproducesone32-bitpackedoutputthatcontain16-bitrealand
16-bitimaginaryvalues.The32x32bitmultiplyinstructionsprovidetheextendedprecisionnecessaryfor
audioandotherhigh-precisionalgorithmsonavarietyofsignedandunsigned32-bitdatatypes.
The.Lor(ArithmeticLogicUnit)nowincorporatestheabilitytodoparalleladd/subtractoperationsona
pairofcommoninputs.Versionsofthisinstructionexisttoworkon32-bitdataoronpairsof16-bitdata
performingdual16-bitaddandsubtractsinparallel.Therearealsosaturatedformsoftheseinstructions.
TheC64x+coreenhancesthe.Sunitinseveralways.IntheC64xcore,dual16-bitMIN2andMAX2
comparisonswereonlyavailableonthe.Lunits.OntheC64x+coretheyarealsoavailableonthe.Sunit
whichincreasestheperformanceofalgorithmsthatdosearchingandsorting.Finally,toincreasedata
packingandunpackingthroughput,the.Sunitallowssustainedhighperformanceforthequad8-bit/16-bit
anddual16-bitinstructions.Unpackinstructionsprepare8-bitdataforparallel16-bitoperations.Pack
instructionsreturnparallelresultstooutputprecisionincludingsaturationsupport.
SubmitDocumentationFeedbackDeviceOverview7