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TMS320C6454
Fixed-PointDigitalSignalProcessor
SPRS311A–APRIL2006–REVISEDDECEMBER2006
C6454RevisionHistory(continued)
SEEADDITIONS/MODIFICATIONS/DELETIONS
Section3.4.2PeripheralConfigurationRegister0Description:
UpdatedparagraphandaddedNote
ChangedallbitfieldresetstoR/W-0andupdatedFigure3-4,PeripheralConfigurationRegister0
(PERCFG0)
UpdatedTable3-7,PeripheralConfigurationRegister0(PERCFG0)FieldDescriptions
Section3.4.5EMACConfigurationRegister(EMACCFG)Description:
Changedbits23:19resetvaluetoR/W-0001bandmovedinRMII_RSTfieldtobit18Figure3-8,EMAC
ConfigurationRegister(EMACCFG)
UpdatedReservedBits31:19DescriptionandRMII_RSTBit18DescriptionValues0and1inTable3-11,
EMACConfigurationRegister(EMACCFG)FieldDescriptions
Section3.7DeletedDebuggingConsiderations
Addednewsection,Pullup/PulldownResistors
Section3.8ConfigurationExamples:
AddedcommentsforAEA[12],AEA[11],andAEA[3]andchangedSYSCLK3toSYSCLK4incommentfor
AEA[4]inFigure3-12,ConfigurationExampleA,andFigure3-13,ConfigurationExampleB
Section5.1MemoryArchitecture:
Updatedparagraphs
UpdatedFigure5-4,TMS320C6454L2MemoryConfigurations
Section6DeviceOperatingConditions:
UpdatedSection6.1,AbsoluteMaximumRatingsOverOperatingCaseTemperatureRange
UpdatedSection6.2,RecommendedOperatingConditions
UpdatedSection6.3,ElectricalCharacteristicsOverRecommendedRangesofSupplyVoltageand
OperatingCaseTemperature
Section7.3.1Power-SupplySequencing:
Updatedparagraph
DeletedPower-SupplySequence(Option1)figureandTimingRequirementsforPower-SupplySequence
(Option1)table
Section7.3.4PreservingBoundary-ScanFunctionalityonRGMIIandDDR2MemoryPinssection:
AddedDV
DD15MON
toparagraphandlist
Section7.4EnhancedDirectMemoryAccess(EDMA3)Controller:
Changed"4QuickDMA(QDMA)channels"to"8QuickDMA(QDMA)channels"
Section7.4.1EDMA3Device-SpecificInformation:
Updatedparagraph
Section7.4.3EDMA3PeripheralRegisterDescription(s):
ChangedTable7-4titletoEDMA3ChannelControllerRegisters
UpdatedHexAddressRangesforParameterSets7,9,254,and255onTable7-5,EDMA3ParameterRAM
AddedTable7-6,EDMA3TransferController0Registers,Table7-7,EDMA3TransferController1
Registers,Table7-8,EDMA3TransferController2Registers,andTable7-9,EDMA3TransferController3
Registers
Section7.5.1InterruptSourcesandInterruptController:
ChangedEventNumber80toReservedinTable7-10,C6454DSPInterrupts
Section7.6ResetController:
UpdatedSystemResetEffect(s),andaddedFootnote(2)inTable7-12,ResetTypes
DeletedSystemResetTimingfigure
Section7.6.7ResetElectricalData/Timing:
UpdatedNote
AddednewFootnote(3)andrenumberedFootnotesto(4)and(5)inTable7-14,TimingRequirementsfor
Reset
Section7.7PLL1andPLL1Controller:
UpdatedFigure7-10,PLL1andPLL1Controller
Section7.7.1PLL1ControllerDevice-SpecificInformation:
UpdatedSYSCLK4bullet
Updatedparagraphs
UpdatedFootnote(1)inTable7-16,PLL1ClockFrequencyRanges
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