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7.10ExternalMemoryInterfaceA(EMIFA)
7.10.1EMIFADevice-SpecificInformation
TMS320C6454
Fixed-PointDigitalSignalProcessor
SPRS311A–APRIL2006–REVISEDDECEMBER2006
TheEMIFAcaninterfacetoavarietyofexternaldevicesorASICs,including:
•Pipelinedandflow-throughSynchronous-BurstSRAM(SBSRAM)
•ZBT(ZeroBusTurnaround)SRAMandLateWriteSRAM
•SynchronousFIFOs
•Asynchronousmemory,includingSRAM,ROM,andFlash
TiminganalysismustbedonetoverifyallACtimingsaremet.TIrecommendsutilizingI/Obuffer
informationspecification(IBIS)toanalyzeallACtimings.
ToproperlyuseIBISmodelstoattainaccuratetiminganalysisforagivensystem,seetheUsingIBIS
ModelsforTimingAnalysisapplicationreport(literaturenumberSPRA839).
Tomaintainsignalintegrity,serialterminationresistorsshouldbeinsertedintoallEMIFoutputsignallines
(fortheEMIFoutputsignals,seeTable2-3,TerminalFunctions).
AraceconditionmayexistwhencertainmasterswritedatatotheEMIFA.Forexample,ifmasterA
passesasoftwaremessageviaabufferinexternalmemoryanddoesnotwaitforindicationthatthewrite
completes,whenmasterBattemptstoreadthesoftwaremessage,thenthemasterBreadmaybypass
themasterAwriteand,thus,masterBmayreadstaledataand,therefore,receiveanincorrectmessage.
Somemasterperipherals(e.g.,EDMA3transfercontrollers)willalwayswaitforthewritetocomplete
beforesignalinganinterrupttothesystem,thusavoidingthisracecondition.Formastersthatdonothave
hardwareguaranteeofwrite-readordering,itmaybenecessarytoguaranteedataorderingviasoftware.
IfmasterAdoesnotwaitforindicationthatawriteiscomplete,itmustperformthefollowingworkaround:
1.Performtherequiredwrite.
2.PerformadummywritetotheEMIFAmoduleIDandrevisionregister.
3.PerformadummyreadtotheEMIFAmoduleIDandrevisionregister.
4.IndicatetomasterBthatthedataisreadytobereadaftercompletionofthereadinstep3.The
completionofthereadinstep3ensuresthatthepreviouswritewasdone.
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