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RGTXCTL, RGRXCTL
MRXER/RMRXER,
MRXDV,
MCRS/RMCRSDV,
MCOL,
MTXEN/RMTXEN
Ethernet MAC (EMAC) and MDIO
MDIO
MDCLK
MDIO
Clock
Clocks
Error Detect
and Control
Input/Output
Receive
RGMDIO
RGMDCLK
RGTXD[3:0]
A. RGMII signals are mutually exclusive to all other EMAC signals.
RGTXC,
RGRXC,
RGREFCLK
MTXD[7:2],
MTXD[1:0]/RMTXD[1:0]
Transmit
RGMII
(A)
GMII
RMII
MII
RGRXD[3:0]
MRXD[7:2],
MRXD[1:0]/RMRXD[1:0]
RGMII
(A)
GMII
RMII
MII
RGMII
(A)
GMII
RMII
MII
RGMII
(A)
GMII
RMII
MII
RGMII
(A)
GMII
RMII
MII
GMII
RMII
MII
RGMII
(A)
MTCLK/RMREFCLK,
MRCLK,
GMTCLK
Ethernet MAC
(EMAC)
TMS320C6454
Fixed-PointDigitalSignalProcessor
SPRS311A–APRIL2006–REVISEDDECEMBER2006
Figure2-10.EMAC/MDIO[MII/RMII/GMII/RGMII]PeripheralSignals
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