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TMS320C6454
Fixed-PointDigitalSignalProcessor
SPRS311A–APRIL2006–REVISEDDECEMBER2006
1TMS320C6454Fixed-PointDigitalSignal5.5MegamoduleResets................................81
Processor..................................................1
5.6MegamoduleRevision...............................82
1.1Features..............................................1
5.7C64x+MegamoduleRegisterDescription(s)........83
1.1.1ZTZ/GTZBGAPackage(BottomView)..............2
6DeviceOperatingConditions........................90
1.2Description............................................2
6.1AbsoluteMaximumRatingsOverOperatingCase
TemperatureRange(UnlessOtherwiseNoted).....90
1.3FunctionalBlockDiagram............................4
6.2RecommendedOperatingConditions...............90
2DeviceOverview.........................................6
6.3ElectricalCharacteristicsOverRecommended
2.1DeviceCharacteristics................................6
RangesofSupplyVoltageandOperatingCase
2.2CPU(DSPCore)Description.........................7
Temperature(UnlessOtherwiseNoted)............92
2.3MemoryMapSummary.............................10
7C64x+PeripheralInformationandElectrical
2.4BootSequence......................................12
Specifications...........................................94
2.5PinAssignments....................................14
7.1ParameterInformation..............................94
2.6SignalGroupsDescription..........................18
7.2RecommendedClockandControlSignalTransition
Behavior.............................................96
2.7TerminalFunctions..................................24
7.3PowerSupplies......................................96
2.8Development........................................47
7.4EnhancedDirectMemoryAccess(EDMA3)
3DeviceConfiguration..................................50
Controller............................................98
3.1DeviceConfigurationatDeviceReset..............50
7.5Interrupts...........................................112
3.2PeripheralConfigurationatDeviceReset...........52
7.6ResetController....................................116
3.3PeripheralSelectionAfterDeviceReset............53
7.7PLL1andPLL1Controller.........................123
3.4DeviceStateControlRegisters.....................55
7.8PLL2andPLL2Controller.........................138
3.5DeviceStatusRegisterDescription.................65
7.9DDR2MemoryController..........................147
3.6JTAGID(JTAGID)RegisterDescription............67
7.10ExternalMemoryInterfaceA(EMIFA).............149
3.7Pullup/PulldownResistors...........................67
7.11I2CPeripheral......................................160
3.8ConfigurationExamples.............................69
7.12Host-PortInterface(HPI)Peripheral...............166
4SystemInterconnect...................................71
7.13MultichannelBufferedSerialPort(McBSP)........177
4.1InternalBuses,Bridges,andSwitchFabrics........71
7.14EthernetMAC(EMAC).............................187
4.2DataSwitchFabricConnections....................72
7.15Timers..............................................205
4.3ConfigurationSwitchFabric.........................74
7.16PeripheralComponentInterconnect(PCI).........207
4.4PriorityAllocation....................................76
7.17General-PurposeInput/Output(GPIO).............214
5C64x+Megamodule....................................77
7.18IEEE1149.1JTAG.................................216
5.1MemoryArchitecture................................77
8MechanicalData.......................................217
5.2MemoryProtection..................................80
8.1ThermalData......................................217
5.3BandwidthManagement............................80
8.2PackagingInformation.............................217
5.4Power-DownControl................................81
RevisionHistory............................................218
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