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Monitor: Basic Operation
Katana®752i User’s Manual 10006024-04
15-6
POST Diagnostic Results
The Katana®752i stores Power-On Self-Test (POST) diagnostic results in I
2
C nonvolatile
random-access memory (NVRAM). This memory is located in the EEPROM at hex address
0x53 on the I
2
C bus. The POST results are stored as a 32-bit value at the hex offset 0x1DD8
of the EEPROM. Each bit indicates the result of a specific test, therefore this field can store
the results of up to 32 diagnostic tests, as described in the following table.
Note: For configurations where the front Ethernet port, eth4, is disabled, the monitor will indicate SKIPPED for the
PCI diagnostic test. This is because the Ethernet controller for eth4 performs the diagnostic testing in this
case. The POST flag for the PCI test will still be set accordingly.
Table 15-3: POST Diagnostics Results
Monitor SDRAM Usage
PPCBoot locates its stack, uninitialized data, and code in the top one megabyte of SDRAM.
The exact address varies with the amount of installed memory. PPCBoot uses the area from
0x00000000 to 0x00004000 in SDRAM for the MPC750 exception vector table and PPC-
Boot internal use.
Caution: Any writes to these areas can cause unpredictable operation of the monitor.
5.344 1000 Monitor code relocated to top of memory
5.978 1001 PCI/cPCI Final Setup. Enumeration. Memory Read/Write Access
6.265 0000 Monitor Prompt
Bit: Diagnostic Test: Value:
0 SDRAM (address and data line integrity) 0=test has passed
1=failure detected
1Flash
2I
2
C access (local I
2
C devices connected to the I
2
C bus)
3 Reserved for Emerson use
4 PCI (known devices present)
5 No EREADY
6 - 23 Reserved for Emerson use
24 - 31 Reserved for customer use
Time
(sec):
Debug LED
State (bits): Monitor State:
!