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Processor: Exception Processing
10006024-04 Katana
®
752i User’s Manual
4-9
EXCEPTION PROCESSING
When an exception occurs, the address saved in Machine Status Save/Restore register 0
(SRR0) helps determine where instruction processing should resume when the exception
handler returns control to the interrupted process. Machine Status Save/Restore register 1
(SRR1) is used to save machine status on exceptions and to restore those values when an rfi
instruction is executed.
When an exception is taken, the 750GL controller uses SRR0 and SRR1 to save the contents
of the Machine State register (MSR) for the current context and to identify where instruc-
tion execution resumes after the exception is handled.
The Machine State register (MSR) configures the state of the 750GL CPU. On initial power-
up of the Katana
®
752i, most of the MSR bits are cleared. Please refer to the IBM PowerPC
documentation for more detailed descriptions of the individual bit fields.
Register 4-4: CPU Machine State (MSR)
POW: Power Management enable. Setting this bit enables the programmable power manage-
ment modes: nap, doze, or sleep. These modes are selected in the HID0 register. This bit
has no effect on dynamic power management.
0= Power management disabled (normal operation mode)
1= Power management enabled (reduced power mode)
ILE: Exception Little-Endian mode.
EE: External interrupt Enable. This bit allows the processor to take an external interrupt, system
management interrupt, or decrementer interrupt.
0= External interrupts and decrementer exception conditions delayed.
1= External interrupt or decrementer exception enabled.
PR: Privilege level.
0= User- and supervisor-level instructions are executed
1= Only user-level instructions are executed
– 00000 Reserved.
01 12 13 14 15
Reserved POW Res. ILE
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EE PR FP ME FE0 SE BE FE1 Res. IP IR DR Res. PM RI LE
Exception:
Vector Address
Hex Offset: Notes: (continued)