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Device Bus PLD: Interrupt Registers
Katana
®
752i User’s Manual 10006024-04
6-2
Register 6-2: Reset Command
SCL: Direct control for I
2
C clock signal:
1=Tri-states the PLD
0=Drives logic low
SDA: Direct control for I
2
C data signal:
1=Tri-states the PLD
0=Drives logic low
PCI0 : PCI0 reset status, as set by JP1, pins 7-8;
software should not overwrite this value:
1=cPCI functionality is disabled
(MV64460 PCI0 interface held in reset)
0=cPCI functionality is enabled
(MV64460 PCI0 interface reset deasserted)
FR: Flash Reset command:
1=Causes Flash to be reset, clears automatically
0=No Flash reset (default)
HR: Hard Reset command:
1=Causes a hard reset on board, clears automatically
0=No hard reset (default)
INTERRUPT REGISTERS
The system error and parity error interrupts from the PCI bus route to the device bus PLD.
Sampling for these signals occurs on the rising edge of the PCI clock, according to the PCI
specification. The software should hold these signals low for a clock cycle, otherwise they
will be ignored. PERR and SERR have two loads, which are combined in the PLD to a single
interrupt and route to the MPP12 pin on the MV64460.
The Interrupt Enable register at hex location F820,2000
16
contains two enable bits, as fol-
lows.
Register 6-3: Interrupt Enable
76543210
SCL SDA PCI0
Reserved
FR Reserved HR
76543210
Reserved SREN PREN